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(Structural ATPG) APAC Digital SOC Test Engineer
(Structural ATPG) APAC Digital SOC Test Engineer
发布于 大约 11 小时前普通员工/个人贡献者
Hsinchu City, Hsinchu City, Taiwan
中级经验
全职员工
仅现场办公
本科
DFT
ATPG
VLSI
ATE
Advantest 93k
Semiconductor
Teradyne Uflex/Iflex
AI 估算 · 80k–120k
Senior role at Qualcomm in Hsinchu's semiconductor hub; competitive compensation for ATPG expertise.
职位详情
关于这个职位
This position focuses on creating test solutions for Qualcomm's SOC products, specifically in Structural ATPG testing. You will work closely with design, DFT, and manufacturing teams to develop ATE code and analyze test data. It offers growth opportunities in digital test engineering within a fast-paced environment.
最低要求
Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
OR
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.
OR
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.
工作职责
As a Product Test Engineer, you will create Automatic Test Equipment (ATE) code/test methods and participate in data reviews which will require close collaboration with Design, Design for Test (DFT), Process, Product, and Manufacturing Engineers.
优先资格
Minimum 2 years of industry experience as a Product Engineer with hands on experience on Advantest 93K or Teradyne UFlex/IFlex.
Understanding of VLSI technologies, familiarity with Digital Baseband products
Proficiency in programming language C/C++/VB/Java/Python is a plus.
Experience with data analytic tools such as O+, Data Power, Exensio and Machine Learning basics will be an added advantage.
Familiarity with Digital Communication concepts. Knowledge of Semiconductor Physics.
Ability to work with common test equipment (oscilloscope, spectrum analyzer, time interval analyzer, logic analyzer, network analyzer, etc).
AI 洞察
优缺点分析
优点
- Work on cutting-edge Qualcomm SOCs with advanced process nodes.
- Strong learning curve in semiconductor test engineering with exposure to full product lifecycle.
- Stable company with global impact and good benefits.
- Fast-paced environment with tight tape-out schedules may require overtime.
- Requires deep technical knowledge and constant learning of new test methodologies.
- Limited remote work flexibility
- on-site presence needed for lab and production support.
- This role is ideal for engineers with a background in digital test or DFT who enjoy hands-on problem-solving and want to work on complex SOCs in a world-class semiconductor company.
缺点 / 挑战
暂无明显挑战项
角色解读
- Deepen expertise in structural test and move into senior DFT or product engineering roles.
- Transition to broader SOC validation or yield enhancement positions.
- Opportunity to lead test strategy for next-generation chip designs.
- Develop and implement ATE test programs for digital SOCs, focusing on structural ATPG patterns.
- Collaborate with DFT and design teams to ensure test coverage and diagnose yield issues.
- Review test data and drive improvements in test time and quality for volume manufacturing.
- Solid understanding of VLSI design and DFT methodologies (scan, ATPG, boundary scan).
- Hands-on experience with ATE platforms like Advantest 93K or Teradyne UFlex/IFlex.
- Programming skills in C/C++ or Python for test automation and data analysis.
申请策略
- Research Qualcomm's SOC products and recent technology announcements to show genuine interest.
- Be prepared to discuss how you approach test coverage optimization and yield improvement.
- Highlight any experience with ATE platforms (93K, UFlex) with specific projects and results.
- Showcase programming projects in C/C++ or Python related to test automation or data analysis.
- Emphasize knowledge of VLSI, DFT, and semiconductor physics from coursework or previous roles.
- Strengthen Python skills for data analytics and scripting.
- Familiarize yourself with industry-standard ATPG tools (e.g., TetraMAX, FastScan) and test pattern formats.
面试指南
- Use STAR method: Situation, Task, Action, Result for behavioral questions.
- For technical questions, start with foundational concepts, then dive into specific examples from your experience.
- Explain the ATPG flow and how you would debug a pattern that fails on the tester.
- Describe your experience with Advantest 93K or Teradyne platforms – what specific features have you used?
- How do you approach reducing test time while maintaining coverage?
- Tell me about a time you collaborated with DFT or design teams to resolve a test issue.
- What is your understanding of scan chain and why is it important?
- Review basic DFT concepts: scan chains, ATPG, fault models (stuck-at, transition).
匹配度报告
64
综合匹配度
Senior IC role at Qualcomm Taiwan with strong technical learning and competitive pay, but limited WLB flexibility.
适合人群
Best suited for candidates motivated by technical skill growth and stable compensation, who are comfortable with on-site work and potential overtime.
最强匹配
成长发展匹配
最弱匹配
工作生活匹配
薪资福利70
成长发展80
工作生活50
使命价值55
薪资福利匹配
70中等
Qualcomm is known for competitive compensation, though the JD does not specify salary or benefits. As a senior IC role in a major semiconductor hub, total package is likely above market average.
薪资信号未披露（AI估算：80K-120K/月）
成长发展匹配
80较高
The role explicitly mentions growth and specialization opportunities in digital test engineering, and the work involves modern ATPG/ATE technologies. Skill development in a leading company is strong.
技术前沿主流现代技术
技术栈ATPG、ATE、VLSI、DFT、C/C++、Python、Advantest 93K、Teradyne UFlex/IFlex
成长机会growth opportunities、specialization opportunities
业务类型ambiguous
工作生活匹配
50较低
The position requires on-site presence in Hsinchu (science park), and while WLB is not mentioned, the fast-paced dynamic environment suggests possible overtime. No remote work indication.
工作模式仅现场办公
办公地点科技园/产业园
加班情况未提及（无法判断）
使命价值匹配
55较低
The work contributes to Qualcomm's SOC products which have global impact, but the role is technical and not directly mission-driven. The semiconductor industry is stable but not high-growth.
行业发展稳定成熟行业
社会影响中性/一般
创新程度积极采用新技术
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