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DRAM Bus and PDN Designer, up to Sr. Staff
DRAM Bus and PDN Designer, up to Sr. Staff
发布于 大约 12 小时前普通员工/个人贡献者
Hsinchu City, Hsinchu City, Taiwan
高级经验
全职员工
仅现场办公
本科
MATLAB
DRAM
Eda Tools
Pdn
2.5D/3D Integration
Bus Design
Mixed-Signal Design
Verilog-Ams
AI 估算 · 40k–60k
Senior engineer at Qualcomm in Hsinchu; semiconductor industry standard with experience premium.
职位详情
关于这个职位
This role focuses on designing high-speed memory bus and power distribution network for custom DRAM used in data center, mobile, and edge computing. You will work with cross-functional teams to optimize bandwidth, latency, and power, and develop simulation models for bus behavior. Ideal for engineers with deep knowledge of DRAM architecture and mixed-signal design.
最低要求
Experience in memory bus design (SRAM/DRAM/Flash/ROM/OPT, etc)
Good knowledge of bus communication protocols
Knowledge of high-speed design principles and reliability
Ability to assess robustness of bus architecture interacting with DRAM bank, PHY, and memory controller
Ability to develop Verilog/Verilog-A/Verilog-AMS models of critical datapath
Experience in mixed-signal design, layout, and simulation
Proficiency in EDA tools, Matlab, and Python
Good knowledge of memory architecture, buses, and 2.5D/3D integration
Master's or Ph.D. in Electrical Engineering and related field
工作职责
Develop and optimize circuits for high-bandwidth memory bus and PDN control, timing, and control
Analyze and ensure signal integrity on bus and PDN across PVT corners
Develop and validate bus behavior for various access protocols to meet throughput, latency, and energy specifications
Develop novel fabrics for robust distribution of high-bandwidth busses and PDN across DRAM array, compute, and IO
Create layouts optimizing bus and PDN placement for routability
Use state-of-the-art design and simulation tools to simulate bus behavior and manufacture readiness
Develop behavioral, timing, and power models of bus to guide architecture choices
Develop power modeling framework for state-dependent power and PMIC requirements
Floorplan 3D DRAM chips under 3D integration constraints, testability, repairability, and high performance
优先资格
Experience in DRAM architecture performance assessment
Experience in programming (C/C++/Python) or scripting (Perl/Python)
Familiar with DRAM datasheets and IO interfaces
AI 洞察
优缺点分析
优点
- Work on cutting-edge custom DRAM for high-performance compute systems.
- Collaborate across multiple teams in a top semiconductor company (Qualcomm).
- High impact: improvements in bandwidth/power directly affect product KPIs.
- Access to advanced EDA tools and 3D integration technologies.
- Requires deep expertise in multiple domains (circuit design, memory architecture, packaging).
- High complexity: optimizing bus and PDN across PVT corners is demanding.
- Potential fast-paced environment with tight product cycles.
- Experienced memory circuit designers who enjoy cross-functional collaboration and want to work on advanced DRAM systems for AI and mobile.
缺点 / 挑战
暂无明显挑战项
角色解读
- Progress to Senior Staff or Principal Engineer leading memory subsystem design.
- Opportunity to shape next-gen memory solutions for AI, mobile, and data center.
- Potential to move into system architecture or technical management roles.
- Design and optimize circuits for high-bandwidth memory bus and power distribution network (PDN) for custom DRAM.
- Simulate bus behavior across PVT corners and ensure signal integrity.
- Develop Verilog/AMS models of critical datapath and power modeling frameworks.
- Collaborate with multiple teams (packaging, AI, SoC) to floorplan 3D DRAM chips.
- Deep expertise in memory bus design (DRAM/SRAM) and high-speed signaling.
- Proficiency in EDA tools, Matlab, Python, and Verilog/AMS for mixed-signal simulation.
- Knowledge of DRAM architecture, bus protocols, and 2.5D/3D integration.
- Strong problem-solving and analytical skills for PVT analysis and layout optimization.
申请策略
- Tailor resume to highlight memory-specific bus/PDN experience, not general ASIC design.
- Network with Qualcomm engineers through industry conferences on memory or EDA.
- Showcase specific projects on memory bus or PDN design, including simulation and layout.
- Highlight experience with Verilog/AMS modeling and EDA tools (e.g., Cadence, Synopsys).
- Emphasize knowledge of DRAM protocols (DDR, HBM) and 2.5D/3D packaging.
- Include any publications or patents related to memory architecture or high-speed design.
- Strengthen Python/Matlab skills for automation and data analysis.
- Learn advanced simulation techniques for signal integrity and power integrity (e.g., HSPICE, HFSS).
面试指南
- Use STAR method: Situation, Task, Action, Result. Focus on specific technical challenges.
- Demonstrate systematic approach: problem definition, analysis (simulation), trade-offs, decision, validation.
- Show cross-functional thinking: consider impact on DRAM array, PHY, controller, and packaging.
- How do you ensure signal integrity in a high-speed memory bus across PVT corners?
- Describe your experience with Verilog-AMS modeling of a mixed-signal block.
- How would you optimize power distribution network for a 3D DRAM stack?
- Explain a challenging memory bus design issue you solved and the trade-offs considered.
- What are the key differences between 2.5D and 3D integration for DRAM?
匹配度报告
69
综合匹配度
Senior DRAM bus/PDN design role at Qualcomm Taiwan, strong technical challenge, moderate compensation, on-site.
适合人群
Engineers prioritizing technical growth and impact over work-life balance.
最强匹配
成长发展匹配
最弱匹配
工作生活匹配
薪资福利80
成长发展85
工作生活40
使命价值70
薪资福利匹配
80较高
Qualcomm offers competitive compensation and benefits typical of a top semiconductor firm. The senior level implies strong salary, but no explicit benefits listed.
薪资信号市场水准 (40K-60K/月)
成长发展匹配
85较高
Working on cutting-edge DRAM and 3D integration provides strong skill growth. Cross-team collaboration enhances learning, but no explicit promotion path mentioned.
技术前沿前沿/新兴技术
技术栈DRAM、2.5D/3D integration、PDN、high-speed design、Verilog-AMS
业务类型ambiguous
工作生活匹配
40较低
On-site work in Hsinchu (science park) likely with standard office hours, but no mention of flexibility or WLB. Expectation of high performance.
工作模式仅现场办公
办公地点科技园/产业园
加班情况未提及（无法判断）
使命价值匹配
70中等
The role contributes to enabling AI and advanced computing, which has societal value. However, direct impact on end-users is indirect.
行业发展高速增长赛道
社会影响正向社会影响力较高
创新程度积极采用新技术
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