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Qualcomm logo
高通
Physical Design Engineer, Senior to Staff Level
立即应聘

Physical Design Engineer, Senior to Staff Level

发布于 大约 12 小时前

普通员工/个人贡献者

Taipei, Taipei City, Taiwan
高级经验
全职员工
仅现场办公
本科
ASIC
SoC
STA
DRC
LVS
TCL
Icc2
Physical Design
Netlist-To-Gdsii

AI 估算 · 25k–45k

Based on senior level, top-tier semiconductor company, and Taiwan market rates for experienced physical design engineers.

职位详情

关于这个职位

As a Physical Design Engineer at Qualcomm, you will be responsible for the complete physical implementation of complex digital integrated circuits (ASICs/SoCs) from netlist to GDSII. You will work on cutting-edge technology nodes (7nm/5nm) using industry-standard EDA tools to optimize timing, power, and area. This role offers the opportunity to contribute to high-performance mobile and computing chips.

最低要求

Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 2+ years of Systems Engineering or related work experience.

OR
Master's degree in Engineering, Information Systems, Computer Science, or related field and 1+ year of Systems Engineering or related work experience.
OR
PhD in Engineering, Information Systems, Computer Science, or related field.

工作职责

Netlist-to-GDSII Implementation: Execute the full physical design flow including Floorplanning, Power Planning, Placement, Clock Tree Synthesis (CTS), and Routing.

Timing Analysis & Closure: Perform Static Timing Analysis (STA) to identify and fix setup/hold violations across various process corners and modes (PVT).
Physical Verification: Run and resolve Design Rule Checks (DRC), Layout vs. Schematic (LVS), and Electrical Rule Checks (ERC) to ensure manufacturability.
Power Optimization: Implement low-power design techniques (multi-voltage, power gating) and analyze IR drop/EM (Electromigration).
Signal Integrity: Analyze and mitigate crosstalk, noise, and signal integrity issues.
Flow Automation: Develop and maintain scripts (Tcl, Shell, Perl, Makefile) to automate design flows and improve efficiency.

AI 洞察

优缺点分析

优点

  • Work on cutting-edge technology nodes (7nm/5nm) with industry-leading tools.
  • Join a global leader in mobile and computing chips with strong R&D investment.
  • Opportunity to develop deep expertise in physical design and sign-off flows.
  • High complexity and pressure to meet aggressive schedules and power/performance targets.
  • Need to constantly learn new tools and methodologies as technology evolves.
  • May involve repetitive iterations for timing closure and verification.
  • Ideal for experienced physical design engineers with a passion for low-level chip implementation and a drive to optimize every transistor.

缺点 / 挑战

暂无明显挑战项

角色解读

  • Progress to Staff or Principal Engineer, owning full-chip design for leading-edge products.
  • Transition to architecture roles focusing on power, performance, and area (PPA) optimization.
  • Move into management leading a physical design team.
  • Transform logical circuit designs into physical layouts using EDA tools like ICC2 and Fusion Compiler.
  • Perform timing closure and power optimization to meet performance and efficiency targets.
  • Run physical verification (DRC/LVS) and ensure manufacturability at advanced nodes.
  • Deep understanding of digital CMOS design, standard cells, and low-power techniques.
  • Proficiency in Synopsys and Mentor EDA tools for physical design and verification.
  • Strong scripting skills in Tcl, Perl, or Shell for flow automation.

申请策略

  • Tailor your resume to emphasize physical design tools and process nodes relevant to Qualcomm's products.
  • Prepare to discuss specific examples of solving complex timing or verification issues.
  • Highlight successful tapeouts and your role in block-level or full-chip implementation.
  • Quantify improvements in timing, power, or area achieved in previous projects.
  • Showcase automation scripts or flow enhancements that improved team productivity.
  • Strengthen knowledge of advanced node challenges (e.g., multi-patterning, EUV).
  • Learn scripting languages like Tcl/Perl if not already proficient.

面试指南

  • Use the STAR method: Situation, Task, Action, Result to provide structured answers.
  • For technical questions, explain the concept, then walk through your thought process and trade-offs.
  • Focus on quantifiable outcomes and learnings from your experiences.
  • Describe your experience with clock tree synthesis and how you balance skew and insertion delay.
  • How do you approach timing closure when facing multiple setup/hold violations across corners?
  • Explain a time you fixed a DRC or LVS violation that seemed unfixable.
  • What low-power techniques have you implemented in previous designs?
  • How do you use scripts to automate parts of the physical design flow?

匹配度报告

69
综合匹配度

Senior physical design role at Qualcomm Taiwan, offering cutting-edge technology exposure but requiring on-site presence and possible odd hours.

适合人群
Best suited for engineers who prioritize technical growth and are comfortable with on-site work and occasional schedule pressure.
最强匹配
成长发展匹配
最弱匹配
工作生活匹配
薪资福利80
成长发展85
工作生活50
使命价值60

薪资福利匹配

80较高

Qualcomm offers competitive compensation and benefits for senior engineers in Taiwan, though specific numbers are not disclosed.

薪资信号未披露(AI估算:25K-45K/月)

成长发展匹配

85较高

The role involves working on leading-edge nodes and complex designs, providing strong technical growth. Training on tools and flows is typically provided.

技术前沿前沿/新兴技术
技术栈Netlist-to-GDSII、STA、ICC2、PrimeTime、low-power、7nm、5nm
业务类型ambiguous

工作生活匹配

50较低

On-site work required in Taipei; typical semiconductor industry may involve some overtime during tapeout deadlines.

工作模式仅现场办公
办公地点科技园/产业园
加班情况未提及(无法判断)

使命价值匹配

60中等

Working for a top semiconductor company on chips that power mobile devices and more provides a sense of contribution to technology advancement.

行业发展稳定成熟行业
社会影响中性/一般
创新程度积极采用新技术
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Created by jianglicat - 讲礼猫

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