高通
CPU Physical Design Engineer, Senior to Senior Staff Level
CPU Physical Design Engineer, Senior to Senior Staff Level
发布于 大约 2 个月前普通员工/个人贡献者
Hsinchu City, Hsinchu City, Taiwan
高级经验
全职员工
仅现场办公
本科
硬件工程
Low Power
CPU
Place And Route
Power Analysis
PPA
TCL
Timing Analysis
AI 估算 · 40k–70k
高级芯片设计工程师，技能稀缺，高通薪资竞争力强，台湾市场水准较高。
职位详情
关于这个职位
This senior CPU Physical Design Engineer role at Qualcomm focuses on leading CPU implementation efforts, including synthesis, place and route, and timing/power signoff. You will collaborate with cross-functional teams to optimize PPA (power, performance, area) for multi-core CPU designs. The position requires deep expertise in low-power and high-performance techniques and scripting (TCL, Python, Perl).
最低要求
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 6+ years of Hardware Engineering, Electrical Engineering, or related work experience. OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 4+ years of Hardware Engineering, Electrical Engineering, or related work experience. OR PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field and 3+ years of Hardware Engineering, Electrical Engineering, or related work experience.
工作职责
Collaborate with cross-functional teams (RTL, Physical Design, Circuits, CAD) to address critical physical design challenges in CPU implementations. Develop innovative techniques within Physical Design and optimization space to meet stringent PPA targets. Coordinate with CPU Software, Architecture, and RTL teams to understand various CPU use cases and propose impactful PPA optimizations. Engage with external CAD tool vendors and internal CAD teams to identify and enhance optimization issues related to CPU designs. Partner with all block-level implementation teams to analyze, implement, and improve optimization methods relevant to the designs. Partner with Process, SoC and Post-silicon teams to analyze, improve design implementations.
优先资格
MS degree in Electrical Engineering with 4+ years of practical experience. Preference for experience in deep submicron process technology nodes. Experience in CPU PPA optimization is advantageous. Knowledge of library cells and optimizations. Solid understanding of industry-standard tools for synthesis, place & route, and tapeout flows. Strong data analytical skills to identify and address physical design issues. Experience in pre-post silicon correlation.
AI 洞察
优缺点分析
优点
- Work on cutting-edge CPU designs for globally impactful Qualcomm products.
- High compensation and benefits typical of top semiconductor companies.
- Opportunity to collaborate with world-class engineers across multiple disciplines.
- Gain deep expertise in advanced process nodes and low-power design.
- High pressure to meet stringent PPA targets under tight schedules.
- Requires continuous learning due to rapidly evolving process technologies and tools.
- Long hours may be required during tapeout crunches.
- Experienced physical design engineers passionate about CPU implementation, who enjoy technical challenges and cross-team collaboration.
缺点 / 挑战
暂无明显挑战项
角色解读
- Move into senior staff or principal engineer roles leading flagship CPU designs.
- Transition into CPU architecture or methodology roles focusing on next-gen technologies.
- Opportunity to lead a team of physical design engineers as a technical lead or manager.
- Lead physical design implementation of CPU cores, including synthesis, floorplanning, placement, routing, and timing/power closure.
- Collaborate with RTL, CAD, and circuit teams to solve complex physical design challenges and meet aggressive PPA targets.
- Develop and improve design methodologies and flows for next-generation CPU implementations.
- Deep knowledge of synthesis, place-and-route, and signoff timing/power analysis tools (e.g., Synopsys, Cadence).
- Proficiency in scripting languages: TCL, Python, Perl for automation and flow development.
- Experience with low-power design techniques and high-performance implementation strategies.
- Strong analytical skills to debug and optimize PPA metrics.
申请策略
- Tailor your resume to match the specific CPU focus, using keywords from the JD.
- Research Qualcomm's latest CPU products (e.g., Kryo) to show genuine interest.
- Emphasize specific CPU or complex SoC tapeout experience, including process node details.
- Showcase PPA optimization achievements with quantitative results (e.g., 15% power reduction).
- List scripting projects that improved flow efficiency or automation.
- Highlight any experience with deep submicron nodes (7nm, 5nm, etc.) and correlation with post-silicon.
- Strengthen TCL/Python scripting skills through hands-on projects.
- Familiarize yourself with Synopsys ICC2 or Cadence Innovus latest features.
面试指南
- Use the STAR method (Situation, Task, Action, Result) to structure your responses.
- Demonstrate systematic problem-solving: define the problem, analyze alternatives, implement solution, and validate.
- Quantify results whenever possible (e.g., 'reduced power by 10% while maintaining frequency').
- Describe a challenging physical design issue you encountered and how you resolved it.
- How do you approach timing closure on a critical path in advanced nodes?
- Explain the impact of process variation on power and performance.
- How would you optimize power without sacrificing performance?
- Tell me about your experience with scripting to automate PD flows.
职位点评
69
综合评分
Senior CPU physical design role at Qualcomm offering top technology and compensation but limited work-life flexibility.
更适合这类人
Tech-driven engineers seeking cutting-edge CPU design challenges and career growth, who can accept on-site work and potential long hours.
表现最好
成长发展
相对薄弱
工作生活
薪资福利80
成长发展85
工作生活40
使命价值70
薪资福利
80较高
High base salary and strong benefits typical of Qualcomm, but exact numbers not disclosed.
薪资信号未披露（AI估算：40K-70K/月）
福利待遇disability accommodation
成长发展
85较高
Cutting-edge CPU technology, collaboration with top teams, and opportunity to innovate.
技术前沿前沿/新兴技术
技术栈CPU、synthesis、place and route、timing、power、low power、deep submicron
成长机会collaborate、innovative、develop innovative techniques
业务类型ambiguous
工作生活
40较低
On-site work in Hsinchu, typical for semiconductor roles; no mention of flexibility.
工作模式仅现场办公
办公地点科技园/产业园
加班情况未提及（无法判断）
使命价值
70中等
Impactful work in enabling next-gen digital experiences, but role is technical and less directly social.
行业发展稳定成熟行业
社会影响中性/一般
使命信号smarter, connected future for all
创新程度积极采用新技术
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