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【Taiwan】APAC Digital SOC Test Engineer-Integration/Structural/ATPG/SCAN/MBIST
【Taiwan】APAC Digital SOC Test Engineer-Integration/Structural/ATPG/SCAN/MBIST
发布于 大约 11 小时前普通员工/个人贡献者
Hsinchu City, Hsinchu City, Taiwan
中级经验
全职员工
仅现场办公
本科
SoC
DFT
ATPG
MBIST
Advantest 93k
Exensio
O+
Teradyne Ultraflex
AI 估算 · 18k–35k
全球领先芯片公司，台湾研发中心，SOC测试技能稀缺，薪资有竞争力。
职位详情
关于这个职位
This role focuses on developing and validating test programs for Qualcomm's SoC and chiplet products, with emphasis on structural test content like ATPG, MBIST, and scan. You will work closely with DFT and design teams to debug test issues, optimize test time, and improve yield, contributing to cutting-edge semiconductor manufacturing at a leading global technology company.
最低要求
Bachelor's or Master's degree in Electrical / Electronic Engineering, Computer Engineering, or a related field.
For senior level, nice to have 4+ years of Test Engineering experience, with hands‑on involvement in SoC test program bring‑up.
Experience in one or more of the following test areas:
Structural test (ATPG, TDF, MBIST)
Functional test
High‑speed test
Test‑related characterization
High‑voltage stress
Integration
Experience in one or more chiplet‑based or multi‑die products, including die‑to‑die (D2D) interfaces and associated test and yield challenges.
Hands‑on experience with Advantest 93K or Teradyne UltraFLEX / iFlex test platforms.
Proficiency in one or more programming or scripting languages (C++, VB, Java, Python).
Experience using test or yield data analysis tools (e.g., O+, Data Power, Exensio).
Exposure to test method or test library development, including development, validation, regression, and enhancements.
工作职责
Develop, bring up, and validate SoC | Chiplet test programs across NPI and high‑volume manufacturing stages.
Debug and resolve issues related to coverage, test time, yield, and test escapes.
Improve test efficiency and cost, including test time optimization and test flow simplification.
Analyze test and yield data to identify trends, root causes, and improvement opportunities.
Collaborate cross‑functionally with DFT, Design, Yield, Reliability, Product, and Manufacturing Test Engineers.
Participate in cross‑region collaboration, driving timely issue resolution across global teams.
Communicate technical findings clearly to peers and stakeholders, with appropriate level of detail.
优先资格
Experience working on System‑on‑Chip (SoC) | Chiplet products.
Experience defining or executing chiplet test strategies, including:
D2D interface coverage
Multi‑stage test flows
Yield issue root‑causing and resolution
Collaboration with DFT, Design, Process, and Package Design teams
Experience supporting test bring‑up or debug on advanced or leading‑edge technology nodes.
Experience using data analysis tools such as O+, Exensio, JMP, or similar platforms.
Experience mentoring or supporting junior engineers in a collaborative engineering environment.
Interest or experience in AI‑assisted tools for test automation, workflow efficiency, or engineering data analysis.
Hands‑on experience with version control systems (Git or SVN).
Familiarity with issue tracking systems such as JIRA.
Comfortable communicating in English, including participation in technical discussions and cross‑region collaboration.
AI 洞察
优缺点分析
优点
- Work at a leading semiconductor company with exposure to cutting-edge technology nodes.
- Opportunity to own critical test content for complex SoC and chiplet products.
- Collaborate with global teams and gain cross-functional experience.
- Competitive compensation and benefits in a stable industry.
- Requires deep technical expertise in structural test
- steep learning curve for newcomers.
- High pressure to meet manufacturing timelines and resolve yield issues quickly.
- Cross-region collaboration may involve time-zone coordination.
- This role is ideal for experienced test engineers who enjoy hands-on debug, data analysis, and working on advanced semiconductor technologies.
缺点 / 挑战
暂无明显挑战项
角色解读
- Progress to Senior Test Engineer with deeper expertise in advanced nodes and chiplet testing.
- Move into DFT or Design roles with broader SoC integration knowledge.
- Lead test strategy for new product introductions and mentor junior engineers.
- Develop and validate test programs for SoC and chiplet products across NPI and high-volume manufacturing.
- Debug structural test issues (ATPG, MBIST) and optimize test time and yield.
- Collaborate with DFT, design, and yield teams to drive data-driven test improvements.
- Analyze test data and communicate findings to cross-regional stakeholders.
- Strong knowledge of structural test methodologies (ATPG, MBIST, scan).
- Hands-on experience with Advantest 93K or Teradyne UltraFLEX test platforms.
- Proficiency in C++, Python, or other scripting languages.
- Familiarity with data analysis tools (O+, Exensio) and version control (Git).
申请策略
- Tailor your resume to the specific test areas mentioned (structural, functional, high-speed).
- Prepare examples of cross-functional collaboration and issue resolution.
- Emphasize hands-on experience with ATPG, MBIST, and scan test on SoC products.
- Highlight proficiency with Advantest 93K or Teradyne test platforms.
- Show examples of test time reduction or yield improvement projects.
- Include programming skills (C++, Python) and data analysis tool usage.
- Deepen knowledge of chiplet test challenges (D2D interfaces, multi-stage flows).
- Learn advanced data analysis platforms like O+ or Exensio if not already familiar.
面试指南
- Use STAR method (Situation, Task, Action, Result) for experience-based questions.
- For technical questions, explain the concept first, then give concrete examples.
- Show systematic problem-solving: define the problem, analyze data, implement solution, verify.
- Describe your experience with ATPG and MBIST test pattern generation and debug.
- How have you optimized test time or improved yield on a previous project?
- Explain the challenges of testing chiplet-based designs versus monolithic SoCs.
- Walk through a complex test program bring-up and how you resolved issues.
- How do you use data analysis to identify test escape root causes?
匹配度报告
66
综合匹配度
Global semiconductor leader, hands-on advanced test engineering, strong learning curve, on-site in Taiwan.
适合人群
This role is best suited for candidates motivated by technical growth and challenging work, who are comfortable with on-site, potentially demanding schedules.
最强匹配
成长发展匹配
最弱匹配
工作生活匹配
薪资福利80
成长发展85
工作生活40
使命价值60
薪资福利匹配
80较高
The position offers competitive compensation and benefits typical of a leading global semiconductor company, though salary is not disclosed. The stability and brand value of Qualcomm add to compensatory motivation.
薪资信号未披露（AI估算：18K-35K/月）
成长发展匹配
85较高
Role provides exposure to cutting-edge technology nodes and chiplet designs, with opportunities to work on advanced test solutions and cross-functional collaboration. Learning opportunities are high.
技术前沿前沿/新兴技术
技术栈ATPG、MBIST、Chiplet、D2D、Advantest 93K、Teradyne UltraFLEX、Python、C++、O+、Exensio
业务类型profit_center
工作生活匹配
40较低
Work is on-site in Hsinchu, Taiwan. No mention of remote work or flexible hours. Semiconductor test roles often involve demanding schedules, especially during tape-out cycles.
工作模式仅现场办公
办公地点科技园/产业园
加班情况未提及（无法判断）
使命价值匹配
60中等
The role contributes to enabling next-generation connected devices, which has broader societal impact. However, the direct social mission is not emphasized in the job description.
行业发展稳定成熟行业
社会影响中性/一般
创新程度积极采用新技术
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