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Qualcomm logo
高通
Senior or Staff IC Packaging Engineer - Mechanical Simulation
立即应聘

Senior or Staff IC Packaging Engineer - Mechanical Simulation

发布于 大约 12 小时前

普通员工/个人贡献者

Hsinchu City, Hsinchu City, Taiwan
中级经验
全职员工
仅现场办公
硕士
FEA
ANSYS
Apdl
Chip-Package Interaction
Solder Joint Reliability
Warpage
Workbench

AI 估算 · 25k–40k

Senior packaging engineer with specialized FEA skills, competitive compensation for semiconductor industry in Taiwan.

职位详情

关于这个职位

This role is for a Senior/Staff IC Packaging Engineer focused on mechanical simulation. You will use FEA (ANSYS) to perform warpage, stress, solder joint reliability, and chip-package interaction analysis for advanced semiconductor packages. You'll work closely with design, NPI, and CPI teams to support high-volume manufacturing and next-generation packaging technologies.

最低要求

Master’s degree in mechanical engineering, Material science, Electrical/Microelectronics, or related engineering field.

+ years of work experience in mechanical FEA analysis for Semiconductor and IC microelectronic packaging industry.
+ years of experience in ANSYS (APDL/Workbench).

工作职责

Develop mechanical FEA models (preferably using ANSYS APDL and Workbench)

Maintain APDL macros/workflows
Establish FEA methodologies/BKM for test correlation, material characterization
Perform stress/mechanical analysis for IC package designs and failure prediction
Warpage/Stress analysis
Solder joint reliability (SJR) prediction
Package assembly process simulation
Chip package interaction (CPI) analysis
Utilize advanced FEA techniques (sub-modeling, contact analysis, non-linear analysis)
Understand fundamentals of silicon, package, and board level interconnect technologies

优先资格

Ph. D degree in Mechanical engineering, Material science, Electrical/Microelectronics, or related engineering field.

+ years of combined experience in Finite Element modeling and Analysis for IC electronic package and interconnects.
+ years of experience in ANSYS (APDL/Workbench).
+ years of direct work experience in Semiconductor and IC microelectronic packaging industry.
Experience with the fundamentals of IC electronic packaging structures, assembly processes, reliability testing and analysis, CPI, Package-Board interaction, and design of experiments (DOE).
Solid understanding of IC packaging materials and their thermo-mechanical behaviors.
Hands-on FEA experience developing and improving BKMs for predictive modeling to guide package mechanical design and support manufacturing and reliability needs.
Experience with material characterization/testing and developing new test methods to improve package FEA model accuracy and prediction correlation.
Research and publications in FEA predictive modeling, Warpage, CPI, and Solder lifetime prediction (plus).
Experience using internal AI tools to accelerate APDL coding and improve simulation workflows (plus).
Strong analytical skills and a proven track record of project execution; excellent communication and presentation skills.
Self-starter with high motivation and a strong commitment to product success; able to work flexible hours to support collaboration across APAC and the U.S.; occasional domestic and international travel may be required.

AI 洞察

优缺点分析

优点

  • Work on cutting-edge semiconductor packaging technologies at a global leader (Qualcomm).
  • Highly specialized skill set in FEA for packaging is in demand across the industry.
  • Collaboration with cross-functional teams provides broad exposure to chip design and manufacturing.
  • Requires deep expertise in both FEA and packaging, which may have a steep learning curve.
  • High expectations for accuracy and timeliness of simulations to support fast-paced product cycles.
  • Occasional need to work flexible hours and travel for collaboration across APAC and U.S.
  • Engineers with a strong background in mechanical FEA and a passion for semiconductor packaging who enjoy solving complex multi-physics problems.

缺点 / 挑战

暂无明显挑战项

角色解读

  • Advance to Principal/Lead Engineer or technical fellow within Qualcomm's packaging engineering ladder.
  • Opportunity to drive R&D for next-generation packaging technologies (e.g., 3D IC, heterogeneous integration).
  • Potential transition to broader roles in chip-package co-design or system-level thermal/mechanical simulation.
  • Build and run finite element models (ANSYS APDL/Workbench) to simulate warpage, stress, and solder joint reliability for IC packages.
  • Collaborate with design, NPI, and CPI teams to provide mechanical simulation insights for current and future chipsets.
  • Develop and maintain FEA methodologies, macros, and best practices to improve prediction accuracy and test correlation.
  • Strong proficiency in ANSYS APDL and Workbench for mechanical FEA.
  • Deep understanding of semiconductor packaging structures, materials, and assembly processes.
  • Experience with advanced FEA techniques (sub-modeling, contact analysis, non-linear analysis) and material characterization.
  • Analytical problem-solving skills and ability to communicate complex simulation results effectively.

申请策略

  • Tailor your resume to include specific projects where your FEA work impacted product design or reliability.
  • During the interview, be prepared to discuss your approach to model validation and correlation with test data.
  • Emphasize hands-on experience with ANSYS APDL/Workbench and specific packaging simulations (warpage, SJR, CPI).
  • Showcase any material characterization or test correlation projects that improved model accuracy.
  • Highlight publications or research in FEA predictive modeling for packaging.
  • Demonstrate ability to work in cross-functional teams and manage multiple projects.
  • If not already proficient, practice ANSYS APDL scripting and Workbench automation.
  • Deepen understanding of semiconductor packaging materials and processes.

面试指南

  • Use STAR method (Situation, Task, Action, Result) for behavioral questions.
  • For technical questions, explain the physics behind the problem, your modeling assumptions, and how you validate results.
  • Describe a complex FEA simulation you performed for an IC package. What challenges did you face and how did you overcome them?
  • How do you ensure your simulation results correlate with actual test data?
  • Explain the key factors affecting solder joint reliability in a flip-chip package.
  • How would you model the warpage of a large organic substrate during reflow?
  • What is your experience with material characterization techniques for packaging materials?
  • Review fundamental concepts in IC packaging: materials, assembly processes, reliability tests.

匹配度报告

70
综合匹配度

Specialized FEA role at Qualcomm Taiwan, strong technical development but on-site and flexible hours required.

适合人群
Candidates who prioritize technical skill growth and cutting-edge technology over strict work-life balance.
最强匹配
成长发展匹配
最弱匹配
工作生活匹配
薪资福利75
成长发展85
工作生活50
使命价值70

薪资福利匹配

75中等

The role offers competitive compensation typical for senior engineers at a top semiconductor company, with base salary and likely benefits. However, exact figures are not disclosed.

薪资信号未披露(AI估算:25K-40K/月)

成长发展匹配

85较高

Strong growth potential due to specialized skills in FEA for advanced packaging, exposure to cutting-edge technologies, and opportunities to publish research.

技术前沿前沿/新兴技术
技术栈FEA、ANSYS、APDL、Workbench、CPI、Solder Joint Reliability
成长机会research and publications、developing new test methods、AI tools
业务类型ambiguous

工作生活匹配

50较低

The job is on-site in Hsinchu, with occasional travel and flexible hours required for global collaboration. Work-life balance may be moderate.

工作模式仅现场办公
办公地点科技园/产业园
加班情况未提及(无法判断)

使命价值匹配

70中等

The role contributes to Qualcomm's chip technology leadership, impacting consumer electronics and wireless communications. Moderate social impact.

行业发展高速增长赛道
社会影响中性/一般
创新程度积极采用新技术
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  • 免费试用
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Created by jianglicat - 讲礼猫

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