高通
Senior IC Packaging Engineer - Mechanical Simulation
Senior IC Packaging Engineer - Mechanical Simulation
发布于 大约 15 小时前普通员工/个人贡献者
Hsinchu City, Hsinchu City, Taiwan
高级经验
全职员工
仅现场办公
硕士
硬件工程
Ansys
Apdl
Ic Packaging
Semiconductor
Solder Joint Reliability
Workbench
Cpi
Fea
AI 估算 · 25k–40k
Senior IC封装工程师，经验要求3+年，Qualcomm全球薪资水平较高，但台湾岗位薪资略低于美国，综合市场估算。
职位详情
关于这个职位
This role focuses on mechanical simulation and FEA analysis for IC packaging at Qualcomm. You will work with cross-functional teams to support advanced packaging technologies, performing stress, warpage, and reliability simulations to guide design and manufacturing decisions.
最低要求
Master’s degree in mechanical engineering, Material science, Electrical/Microelectronics, or related engineering field.
+ years of work experience in mechanical FEA analysis for Semiconductor and IC microelectronic packaging industry.
+ years of experience in ANSYS (APDL/Workbench).
工作职责
Develop mechanical FEA models (preferably using ANSYS APDL and Workbench), maintain APDL macros/workflows, establish FEA methodologies/BKM for test correlation, material characterization, and performing stress/mechanical analysis for IC package designs and failure prediction. Responsibilities include but are not limited to: Warpage/Stress analysis, Solder joint reliability (SJR) prediction, package assembly process simulation, and chip package interaction (CPI) analysis.
优先资格
Ph. D degree in Mechanical engineering, Material science, Electrical/Microelectronics, or related engineering field.
+ years of combined experience in Finite Element modeling and Analysis for IC electronic package and interconnects.
+ years of experience in ANSYS (APDL/Workbench).
+ years of direct work experience in Semiconductor and IC microelectronic packaging industry.
Experience with the fundamentals of IC electronic packaging structures, assembly processes, reliability testing and analysis, CPI, Package-Board interaction, and design of experiments (DOE).
Solid understanding of IC packaging materials and their thermo-mechanical behaviors.
Hands-on FEA experience developing and improving BKMs for predictive modeling to guide package mechanical design and support manufacturing and reliability needs.
Experience with material characterization/testing and developing new test methods to improve package FEA model accuracy and prediction correlation.
Research and publications in FEA predictive modeling, Warpage, CPI, and Solder lifetime prediction (plus).
Experience using internal AI tools to accelerate APDL coding and improve simulation workflows (plus).
Strong analytical skills and a proven track record of project execution; excellent communication and presentation skills.
Self-starter with high motivation and a strong commitment to product success; able to work flexible hours to support collaboration across APAC and the U.S.; occasional domestic and international travel may be required.
AI 洞察
优缺点分析
优点
- Work on cutting-edge semiconductor packaging technologies for Qualcomm's leading chipsets.
- High visibility role with exposure to multiple teams (design, NPI, CPI).
- Strong compensation and benefits from a top-tier multinational company.
- Opportunity to develop deep expertise in FEA and mechanical simulation.
- Requires strong analytical skills and ability to handle complex, non-linear simulations.
- Must work flexible hours to collaborate across APAC and US time zones.
- Occasional travel may be required
- high expectations for project execution.
- This role is ideal for an experienced mechanical simulation engineer with a passion for semiconductor packaging and a desire to impact product quality and reliability.
缺点 / 挑战
暂无明显挑战项
角色解读
- Become a technical expert in IC packaging simulation, leading methodology development for next-gen packages.
- Move into technical leadership or management roles within packaging engineering.
- Expand into broader chip-package-system co-design or advanced packaging technologies.
- Develop and run finite element analysis (FEA) models for IC package warpage, stress, and solder joint reliability.
- Collaborate with design, NPI, and CPI teams to provide simulation support and guide package design decisions.
- Establish and improve simulation methodologies, material characterization, and correlation with test data.
- Strong proficiency in ANSYS APDL and Workbench for mechanical FEA.
- Deep understanding of IC packaging structures, materials, and assembly processes.
- Experience with semiconductor reliability testing and failure analysis.
- Excellent communication and cross-functional collaboration skills.
申请策略
- Tailor your resume to reflect direct experience in semiconductor packaging FEA, using keywords from the job description.
- Prepare to discuss specific examples of simulation projects that improved package reliability or design.
- Emphasize hands-on FEA experience with ANSYS APDL/Workbench and specific IC packaging simulations.
- Highlight any experience in material characterization, test correlation, and methodology development.
- Showcase publications, patents, or contributions to predictive modeling in packaging.
- Demonstrate cross-functional collaboration and project execution skills.
- Deepen knowledge of IC packaging materials and thermo-mechanical behavior.
- Familiarize with AI tools for accelerating simulation workflows (desired).
面试指南
- Use the STAR method (Situation, Task, Action, Result) for behavioral questions.
- For technical questions, explain the problem, your approach, the tools used, and the outcome with quantifiable results.
- Demonstrate your thought process: how you set up the model, assumptions, boundary conditions, and validation.
- Describe your experience with ANSYS APDL and Workbench for IC packaging simulation.
- How do you approach material characterization and model correlation for warpage analysis?
- Explain a time you used FEA to solve a complex packaging reliability issue.
- How do you handle cross-functional collaboration with design and NPI teams?
- What is your experience with chip-package interaction (CPI) analysis?
职位点评
71
综合评分
Top-tier semiconductor packaging simulation role with strong technical growth, competitive pay, but demanding schedule and global collaboration.
更适合这类人
This role is best suited for candidates who prioritize technical growth and impact over work-life balance, and are comfortable with on-site work and flexible hours.
表现最好
成长发展
相对薄弱
工作生活
薪资福利80
成长发展85
工作生活50
使命价值70
薪资福利
80较高
Qualcomm offers competitive compensation and benefits, especially for senior roles. However, the salary level in Taiwan may be slightly lower than US counterparts, still above market average in Taiwan.
薪资信号未披露（AI估算：25K-40K/月）
福利待遇diversity support、reasonable accommodations
成长发展
85较高
The role provides opportunities to work on cutting-edge packaging technologies and develop deep FEA expertise. Strong growth signals from collaboration with multiple teams and potential to lead methodology.
技术前沿主流现代技术
技术栈ANSYS、APDL、Workbench、FEA、IC Packaging、CPI
业务类型ambiguous
工作生活
50较低
The role is on-site in Hsinchu and requires flexible hours to support global collaboration. Occasional travel is required, impacting work-life balance.
工作模式仅现场办公
办公地点科技园/产业园
加班情况JD含高强度暗示词
使命价值
70中等
Working at Qualcomm on advanced packaging contributes to mobile and IoT innovation. The semiconductor industry is stable with moderate growth, and the role has a positive impact on product reliability.
行业发展稳定成熟行业
社会影响中性/一般
使命信号support diversity
创新程度积极采用新技术
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