Own the end to end power architecture for x86 platforms (desktop, notebook, or server), spanning APU/CPU, memory, chipset, PCIe, and auxiliary power rails.
Design, simulate, and optimize high-efficiency DC-DC power solutions for battery life and high-performance CPU/APU platforms.
Schematic design, PCB layout reviews, and component selection to meet power delivery requirement (e.g., voltage ripple, transient response, efficiency etc.).
Collaborate with cross-functional teams (Arch, EE, thermal, layout, SI/PI etc.) to delivery motherboard reference board on time.
Conduct PDN (power delivery network) simulation and analysis, ensure power integrity.
Handle system-level power optimization, from platform hardware (SoC, display, WIFI, SSD, charger, connectivity etc.) to firmware (BIOS/UEFI, EC), ensuring superior battery life.
Perform full stack idle power breakdown, measurement, and bottleneck identification.
Own battery life KPI improvements across platform/silicon/firmware/system layers.
Improve VR/PDN light load efficiency and cooperate with power architecture teams.
Drive display idle power optimization through PSR, DCN, refresh rate and driver improvements.
Drive WLAN/SSD/EC/IO idle consumption via driver/firmware tuning.
Drive BIOS/firmware low power feature implementation and tuning.
Drive battery technology related research to enhance battery life.
Lead cross team battery life validation, regression, and optimization.
Optimize SoC C states / G states / P states and enhance idle residency.
Collaborate closely with silicon power architects to translate SoC power requirements (VID tables, SVI/VR protocols, transients, efficiency targets, low power states) into robust platform level solutions.