博通
R&D Physical Design Engineer
R&D Physical Design Engineer
发布于 大约 8 小时前普通员工/个人贡献者
上海市
高级经验
全职员工
仅现场办公
硕士
硬件工程
ASIC
STA
DRC
LVS
TCL
VLSI
Physical Design
7Nm
AI 估算 · 40k–60k
博通为国际芯片巨头，上海高级物理设计工程师薪资具有竞争力，7年以上经验+先进制程技能稀缺，月薪可达40-60K。
职位详情
关于这个职位
作为博通研发中心的物理设计工程师，你将参与先进制程（7nm及以下）芯片的物理实现，包括布局规划、时序收敛、物理验证等关键环节
该职位要求扎实的VLSI背景和独立处理模块/顶层任务的能力，适合希望在芯片后端设计领域深入发展的技术专家
最低要求
Candidates should have good understanding about ASIC design flow and solid VLSI background.
Candidates should be able to handle block implementation/top level task independently.
Tapeout experience in 7nm and blow process design.
Candidates should have strong communications and problem solving skills.
Candidate is good at Perl/Tcl
Education: 7+ years MS Preferred; Major: Microelectronics or related discipline
工作职责
Physical Design Implementation including floor planning, placement, design closure, STA, and DRC & LVS
Develop skills in the above areas
Handle block implementation/top level task independently
Run full chip signoff tasks including PI, SI, PV and STA（preferred）
优先资格
DFT insertion
Power/IVD analysis
DRC/LVS
STA
AI 洞察
暂无 AI 洞察数据
匹配度报告
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