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ISP designer, Sr.

ISP designer, Sr.

发布于 大约 14 小时前

普通员工/个人贡献者

Taipei, Taipei City, Taiwan
高级经验
全职员工
仅现场办公
本科
硬件工程
Architecture
Asic Design
Isp
Low Power
Rtl
Soc
Virtuoso

AI 估算 · 35k–55k

Senior ISP ASIC design at a leading semiconductor innovator, scarce skill set, strong market demand and competitive pay.

职位详情

关于这个职位

As a senior ISP designer at Qualcomm, you will define, architect, and verify high-performance, low-power ASIC IP for image signal processing. You will collaborate with cross-functional teams to shape product execution, guide junior engineers, and influence key technical decisions. This role requires deep ASIC design expertise and a passion for pushing technology boundaries.

最低要求

Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.

OR
Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.

工作职责

Leverages advanced ASIC knowledge and experience to define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power products.

Creates advanced architectures, circuit specifications, logic designs, and/or system simulations based on system-level requirements.
Collaborates across functional teams (e.g., software architecture, hardware architecture, product management, program management teams) to develop and execute an implementation strategy that meets system requirements and customer needs.
Evaluates all aspects of complex process flow from high-level design to synthesis, place and route, timing and power use, and verification or similarly for custom circuit design/layout flow.
Utilizes tools/applications (e.g., RTL to GDS Flow, Virtuoso) to execute and enable advanced architecture and design of multiple complex blocks/SoC or IC Packages.
Writes and reviews detailed technical documentation for complex EDA/IP/ASIC projects.

优先资格

Master's degree in Electrical/Electronic Engineering, Computer Engineering, or Computer Science.

+ years of ASIC design, verification, validation, integration, or related work experience.
+ years of experience with architecture and design tools.
+ years of experience with scripting tools and programming languages.
+ years of experience with design verification methods.
+ year of work experience in a role requiring interaction with senior leadership (e.g., Director level and above).

AI 洞察

优缺点分析

优点

  • Work at Qualcomm, a leading innovator in the semiconductor industry, on cutting-edge low-power ASIC designs.
  • High degree of independence and decision-making responsibility, with a role that influences key technical directions.
  • Competitive compensation and opportunities for career growth.
  • Complex and demanding technical scope, requiring expertise across multiple aspects of ASIC design.
  • May require occasional high-pressure work to meet project milestones.
  • Must collaborate with diverse teams and interact with senior leadership, demanding strong communication skills.
  • This role is ideal for experienced ASIC engineers with deep technical expertise and a desire to take on technical leadership responsibilities while continuing hands-on design work.

缺点 / 挑战

暂无明显挑战项

角色解读

  • Progress to lead ASIC architect or technical manager, overseeing larger IP/SoC development initiatives.
  • Opportunity to influence key organizational decisions and mentor junior engineers, building leadership capabilities.
  • Potential to expand into broader hardware engineering leadership roles within Qualcomm or the industry.
  • Design and develop high-performance ASIC IP for image signal processing, covering architecture, RTL, verification, and implementation.
  • Collaborate with cross-functional teams (software, hardware, product) to define execution strategies that meet system requirements.
  • Supervise and guide junior engineers, and write detailed technical documentation for complex EDA/IP/ASIC projects.
  • Deep knowledge of ASIC design flow (RTL to GDS), including synthesis, timing, and power optimization.
  • Experience with design tools like Virtuoso, and scripting languages such as Python or Perl.
  • Strong understanding of low-power design techniques and verification methodologies.
  • Excellent communication and negotiation skills, with the ability to interact with senior leadership.

申请策略

  • Emphasize your alignment with Qualcomm's mission of enabling smarter, connected experiences.
  • Be prepared to discuss your experience in collaborating with cross-functional teams and handling complex technical decisions.
  • Highlight your experience with ISP or similar high-performance/low-power ASIC designs.
  • Showcase your ability to lead technical tasks and mentor team members.
  • Include specific examples of complex designs you delivered, and your proficiency with design tools and scripting.
  • If you lack ISP knowledge, study image signal processing and camera pipeline concepts.
  • Refresh your skills in advanced verification methodologies and low-power design techniques.
  • Improve your scripting and automation skills (Python, TCL) for design efficiency.

面试指南

  • Use the STAR method (Situation, Task, Action, Result) to structure your answers, focusing on your role and quantifiable outcomes.
  • For technical design questions, walk through your process: requirements analysis, architecture trade-offs, implementation details, and verification.
  • For leadership questions, demonstrate your ability to balance technical depth with team guidance.
  • Describe a complex ASIC design project you worked on
  • what challenges did you face and how did you overcome them?
  • How would you approach designing a low-power ISP block for a mobile SoC?
  • Explain your experience with verification strategies for high-performance ASICs.
  • How have you mentored or supervised less experienced team members?

职位点评

78
综合评分

Senior ISP ASIC design role at Qualcomm, offering strong technical development and compensation, but limited work-life balance signals.

从薪资福利、成长空间、工作节奏和岗位方向综合评估,方便横向比较。

更适合这类人
This role is best for engineers who crave technical challenges and career growth, and can tolerate an on-site position with uncertain work-life balance.
表现最好
成长发展
相对薄弱
工作生活
薪资福利85
成长发展88
工作生活60
使命价值70

薪资福利

85较高

Qualcomm offers competitive compensation and benefits typical of a multinational semiconductor leader, making this role financially rewarding.

薪资信号未披露(AI估算:35K-55K/月)

成长发展

88较高

This role provides exposure to cutting-edge ASIC design and significant technical challenges, enabling rapid skill development and potential career advancement.

技术前沿主流现代技术
技术栈ASIC、RTL、SoC、Low power、ISP、Verification、Virtuoso、Python
业务类型ambiguous

工作生活

60中等

The role is on-site in Taipei with no explicit work-life balance policies mentioned; typical ASIC design jobs can involve periods of intense workload.

工作模式仅现场办公
办公地点未明确
加班情况未提及(无法判断)

使命价值

70中等

Qualcomm's mission to create a smarter, connected future adds a sense of purpose, but the specific role is primarily technical execution.

行业发展稳定成熟行业
社会影响中性/一般
使命信号to help create a smarter, connected future for all
创新程度积极采用新技术
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