高通
SerDes high speed IP ATE Test Development & Characterization Engineer, up to Sr.
SerDes high speed IP ATE Test Development & Characterization Engineer, up to Sr.
发布于 大约 11 小时前普通员工/个人贡献者
Hsinchu City, Hsinchu City, Taiwan
高级经验
全职员工
仅现场办公
本科
信号完整性
SERDES
PCIe
VLSI
ATE测试
USB
UFS
Advantest 93000
AI 估算 · 20k–35k
Senior ATE engineer at Qualcomm in Taiwan; competitive base salary plus benefits.
职位详情
关于这个职位
This role involves developing ATE test solutions for high-speed SerDes IPs (PCIe, UFS, USB, etc.) on Advantest 93000 platform. You will work closely with design, system, and bench teams to validate and characterize silicon, debug issues, and support volume production. The position offers exposure to cutting-edge VLSI and mixed-signal testing in a leading semiconductor company.
最低要求
Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
OR
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.
OR
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.
工作职责
Develop ATE test solutions for production, design validation and characterization.
Work on Advantest 93000 tester platform, covering SerDes PHYs such as PCIe, UFS, USB2/3/4, DSI, CSI, and in-house proprietary high speed IP.
Collaborate with design, system, bench and vector teams to bring up ATE test cases, debug silicon issues.
Work with hardware team to develop ATE test to meet production requirements.
Support volume production including test time reduction and yield issue debug.
Drive failure analysis to completion with across stakeholders.
优先资格
Knowledge of Electrical/Electronic engineering fundamentals, digital, analog, mixed-signal and VLSI.
Knowledge of computer programming fundamentals (C/C++/Java/Perl)
Knowledge of signal integrity concepts
Knowledge of SERDES IP working fundamentals (CTLE, CDR, etc.)
Experience with the Advantest 93000 platform or other ATE platform
Knowledge of statistical concepts, analysis and techniques.
Knowledge in test automation development/scripting/debugging is a plus.
Strong verbal and written communications skills.
Independent, initiative and ability to overcome technical challenges.
Good organization and documentation skills.
AI 洞察
优缺点分析
优点
- Work on cutting-edge SerDes technology used in flagship mobile and automotive chips.
- Strong company reputation and resources for professional development.
- Collaboration with global teams across design and bench, providing broad exposure.
- High complexity of debugging high-speed mixed-signal issues under tight schedules.
- Requires deep technical knowledge across multiple domains (ATE, signal integrity, programming).
- Potential for fast-paced production support with pressure to reduce test time.
- Engineers passionate about hardware validation and ATE, with strong EE fundamentals and problem-solving skills.
缺点 / 挑战
暂无明显挑战项
角色解读
- Progress to senior test engineer or lead characterization projects.
- Transition to design validation or system-level roles.
- Become an expert in high-speed interface testing and methodology.
- Develop and debug ATE test programs for high-speed SerDes IP on Advantest 93000 platform.
- Collaborate with design and bench teams to validate silicon and resolve issues.
- Optimize test time and yield for volume production.
- Strong background in digital/analog/mixed-signal circuits and VLSI.
- Proficiency in programming languages like C/C++ and Perl for test automation.
- Hands-on experience with ATE testers, especially Advantest 93000.
- Knowledge of SerDes architecture, CTLE, CDR, and signal integrity.
申请策略
- Tailor resume to highlight relevant hardware validation experience and use keywords like 'ATE', 'SerDes', 'PCIe'.
- Research Qualcomm's latest products and SerDes IP to show genuine interest.
- Emphasize ATE experience, especially with Advantest 93000 or similar platforms.
- Detail projects involving SerDes, high-speed interfaces, or mixed-signal testing.
- Showcase programming skills in C/C++/Perl and any test automation scripts.
- Deepen knowledge of SerDes fundamentals (CTLE, CDR, DFE) via online courses or textbooks.
- Practice with Advantest 93000 programming if possible.
- Learn statistical analysis for yield and test time optimization.
面试指南
- For debugging questions, use a structured approach: isolate the issue -> analyze waveforms/datalogs -> compare with expected behavior -> consult design/bench teams.
- For technical concepts, define terms briefly, then give an example from your experience. Show depth but stay concise.
- For process questions, describe a specific project where you improved test time or yield, quantifying results.
- Explain how you would debug a failing high-speed SerDes test on ATE.
- Describe your experience with Advantest 93000 platform and its capabilities.
- How do you approach test time reduction without compromising coverage?
- What is the role of CTLE and CDR in a SerDes receiver?
- How would you correlate ATE results with bench characterization data?
匹配度报告
68
综合匹配度
Senior SerDes ATE engineer role at Qualcomm Taiwan: cutting-edge tech, strong development opportunities, but on-site and WLB uncertain.
适合人群
This role is best for engineers who prioritize technical growth and career development in high-speed digital testing, and are comfortable with on-site work and potential for overtime.
最强匹配
成长发展匹配
最弱匹配
工作生活匹配
薪资福利75
成长发展85
工作生活50
使命价值60
薪资福利匹配
75中等
The role offers competitive compensation typical of a senior engineer at a top semiconductor company in Taiwan. However, the JD does not specify exact salary or benefits.
薪资信号未披露（AI估算：20K-35K/月）
成长发展匹配
85较高
Strong opportunity to work with cutting-edge SerDes technology and advanced ATE platforms. The role involves collaboration with multiple teams, offering significant learning potential. Minor: no explicit mention of training or mentorship.
技术前沿前沿/新兴技术
技术栈SerDes、PCIe、UFS、USB、Advantest 93000、CTLE、CDR、VLSI
业务类型ambiguous
工作生活匹配
50较低
Work is on-site (lab/fab environment) with no mention of remote options. Taiwan semiconductor industry typically expects some overtime during tape-out periods but JD doesn't specify. Office location likely in Hsinchu Science Park.
工作模式仅现场办公
办公地点科技园/产业园
加班情况未提及（无法判断）
使命价值匹配
60中等
Working on high-speed IPs that enable next-gen wireless and computing contributes to technological advancement, but JD lacks explicit mission-driven language. Industry is stable but not high-growth in terms of social impact.
行业发展稳定成熟行业
社会影响中性/一般
创新程度积极采用新技术
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