Silicon Design Engineer

该职位是AMD上海CIT团队的高级数字设计工程师，负责chiplet互连IP的RTL设计、微架构定义与实现

Defining and implementing the RTL of a new AMD chiplet interconnect IP. Participate in RTL implementation for functional blocks of the IP. Optimize RTL implementation from implementation perspective in cooperation with RTL and Architecture teams. Optimization of physical implementation in cooperation with Physical Design team. Synthesis, Equivalence Checking, Clock-Domain Crossing (CDC) Analysis, Area/Power optimizations, Linting, Static Timing Analysis (STA).

Experience in digital front-end implementation, including micro-arch. definition. Experience with state-of-the-art industry standard digital tools. RTL design experience with multi-clock, high frequency designs. Knowledge in digital RTL Design and Implementation. Basic understanding in high-speed I/O protocols (PCIe, UCIe…).