思科
Memory Layout Engineer
Memory Layout Engineer
发布于 大约 19 小时前普通员工/个人贡献者
ZHUBEI, Hsinchu County, Taiwan
中级经验
全职员工
仅现场办公
本科
硬件工程
Drc
Erc
Lvs
Memory Layout
Sram
Tcam
Virtuoso
AI 估算 · 25k–40k
Based on 3+ years experience in hardware memory layout at a multinational like Cisco in Taiwan, market salary for this level is
职位详情
关于这个职位
This role focuses on designing and optimizing advanced SRAM/TCAM macro layouts for next-generation networking products. You will work closely with circuit and physical design teams to ensure DRC/LVS/ERC signoff and drive first-pass silicon success. The position offers exposure to leading-edge process nodes and the opportunity to mentor junior team members.
最低要求
Bachelor’s degree in Electrical Engineering, Computer Science, or a related field.
+ years of professional experience in embedded memory layout.
Proficiency with the Virtuoso layout editor (or other similar EDA tool)
Experience with physical verification tools such as Calibre (DRC/LVS/ERC) or other similar tool
Strong communication skills and a positive mindset.
工作职责
Design and optimize advanced SRAM/TCAM macro layouts for next-generation products.
Ensure DRC/LVS/ERC signoff and drive first-pass silicon success.
Collaborate with circuit, verification, and physical design teams to resolve layout issues and integrate solutions.
Promote layout best practices and support innovation on leading-edge process nodes.
Mentor junior team members and help achieve key project milestones.
优先资格
Master’s degree in Electrical Engineering, Computer Science, or a related field.
Experience working with advanced technology nodes.
Demonstrated ability to collaborate effectively in cross-functional teams.
Proven track record of successful project delivery in embedded memory layout.
AI 洞察
优缺点分析
优点
- Work on advanced networking chips at a leading tech company (Cisco).
- Gain deep expertise in memory layout and physical verification at advanced nodes.
- Opportunity to mentor and shape team practices, enhancing leadership skills.
- Stable environment with global impact and competitive compensation.
- High precision work with strict DRC/LVS requirements can be demanding.
- Requires continuous learning as process nodes evolve rapidly.
- Collaboration across multiple teams may involve complex coordination.
- This role is ideal for experienced memory layout engineers who enjoy hands-on physical design, have a keen eye for detail, and want to work on high-performance chips in a collaborative environment.
缺点 / 挑战
暂无明显挑战项
角色解读
- Progress to Senior Memory Layout Engineer or Lead Layout Engineer, owning complex blocks.
- Transition into circuit design or CAD engineering roles with broader chip design exposure.
- Move into management as a layout team lead or project manager within the silicon organization.
- Design and optimize SRAM/TCAM macro layouts for cutting-edge networking chips.
- Run physical verification (DRC/LVS/ERC) to ensure manufacturability.
- Collaborate with circuit designers and CAD teams to resolve layout issues.
- Mentor junior engineers and promote best practices in layout design.
- Proficiency in EDA tools like Virtuoso for custom layout design.
- Experience with physical verification tools such as Calibre.
- Deep understanding of memory architectures (SRAM/TCAM) and process nodes.
- Strong communication and teamwork skills in a cross-functional environment.
申请策略
- Read about Cisco's Silicon One architecture to show genuine interest.
- Prepare examples of complex layout problems you solved and how you contributed to tapeout success.
- Showcase specific SRAM/TCAM layout projects and your role in DRC/LVS closure.
- Highlight proficiency in Virtuoso and Calibre, including any advanced node experience.
- Mention cross-team collaboration and mentoring experiences.
- Include any patents or publications related to memory design.
- If not familiar with leading-edge processes, study FinFET or GAA layout techniques.
- Strengthen scripting skills (e.g., SKILL, Python) to automate layout verification tasks.
面试指南
- Use the STAR method: situation, task, action, result.
- For technical questions, walk through your thought process step by step, mentioning tools and techniques used.
- Emphasize collaboration and communication skills in cross-functional settings.
- Describe a challenging SRAM layout you worked on and how you resolved DRC issues.
- How do you approach LVS debugging when there is a mismatch?
- Explain your experience with advanced process nodes and specific layout constraints.
- How do you collaborate with circuit designers to optimize layout for performance?
- Tell me about a time you mentored a junior engineer and helped them improve.
职位点评
66
综合评分
Hardware memory layout role at Cisco Taiwan focusing on advanced SRAM/TCAM designs with good growth potential but limited flexibility.
更适合这类人
This role is best for candidates who prioritize technical skill growth and working on cutting-edge hardware, and who are comfortable with an on-site work environment.
表现最好
成长发展
相对薄弱
工作生活
薪资福利75
成长发展80
工作生活50
使命价值60
薪资福利
75中等
Cisco offers competitive base salary and benefits typical of a large multinational. The salary in Taiwan is decent but not top-tier compared to Silicon Valley.
薪资信号未披露（AI估算：25K-40K/月）
成长发展
80较高
The role provides strong technical growth in advanced memory layout and process nodes. Mentoring and collaboration opportunities also support career development.
技术前沿前沿/新兴技术
技术栈SRAM、TCAM、Virtuoso、Calibre、DRC、LVS、ERC
成长机会mentor junior team members
业务类型ambiguous
工作生活
50较低
The job is fully on-site in Zhubei, Taiwan, with no mention of flexible hours or remote work. The location is a tech hub, but work-life balance signals are absent.
工作模式仅现场办公
办公地点科技园/产业园
加班情况未提及（无法判断）
使命价值
60中等
Working on networking chips for Cisco contributes to global connectivity and data infrastructure. The impact is significant but not directly tied to social or environmental causes.
行业发展高速增长赛道
社会影响中性/一般
创新程度积极采用新技术
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