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思科
FA Engineering Technical Leader

FA Engineering Technical Leader

发布于 大约 2 小时前

普通员工/个人贡献者

Taipei, New Taipei, Taiwan
专家级经验
全职员工
仅现场办公
本科
质量保证
Asic
Ate
Cross Section
Csam
Failure Analysis
Fib
Jedec
Mbist
Root Cause Analysis

AI 估算 · 40k–60k

思科为国际巨头,台湾高薪,资深ASIC失效分析专家稀缺,月薪预计4-6万人民币。

职位详情

关于这个职位

You will be part of Cisco's Quality and Reliability team, performing failure analysis of ASIC products. You will conduct root cause analysis, develop FA processes, and collaborate with cross-functional teams to ensure product reliability.

最低要求

Bachelors degree in Electrical/Electronics Engineering or related required. Masters preferred.

+ years of experience in semiconductor failure analysis field.
Proven ability to write and execute FA plans and interpret results from FA techniques such as cross section, X-ray, CSAM, TDR, FIB, SEM, and TEM, IR/EMMI/OBIRCH.
Proven ability to specify hardware and implement set up for dynamic FA using SIL (Solid Immersion Lens) and LSM (Laser Scanning Microscopy).
Working knowledge of fault isolation techniques using ATE, Scan/ATPG, MBIST to identify, isolate and characterize device-level faults.

工作职责

Conduct root cause failure analysis of silicon product reliability test and field failures and propose corrective actions.

Develop and implement standard processes for failure analysis using all types of FA techniques and equipment.
Coordinate all the logistics and instructions to direct the failure analysis process and carry out FA function in a systematic way.
Document and report failure analysis results to management.
Function as a technical resource for failure analysis questions.
Develop and maintain relationships with FA service and equipment vendors.

优先资格

Semiconductor technology and process knowledge (Fab, Assembly, and Advanced Packaging).

Good understanding of transistor function/basic electronics, semiconductor device physics and behavior under various operating conditions
Knowledge of JEDEC IC Qualification tests and requirements is beneficial.
Experience with semiconductor frontend fabrication, backend assembly, ASIC testing, and discrete component failure analysis.
Proven experience driving physical failure analysis with suppliers.

AI 洞察

优缺点分析

优点

  • Opportunity to work with cutting-edge semiconductor failure analysis technologies and equipment.
  • Global networking and collaboration with multiple engineering teams at a leading tech company.
  • High compensation package and benefits typical for multinational corporations in Taiwan.
  • Challenging and intellectually stimulating work with potential for significant technical impact.
  • Requires 10+ years of specialized experience, making entry difficult for junior engineers.
  • Heavy reliance on laboratory work and hands-on activities, which may be physically demanding.
  • Need to stay updated with rapidly evolving semiconductor packaging and fault isolation techniques.
  • Ideal for experienced semiconductor failure analysis engineers who are passionate about root cause analysis and enjoy hands-on lab work in a collaborative, fast-paced environment.

缺点 / 挑战

暂无明显挑战项

角色解读

  • Progress within the technical track to become a distinguished engineer or technical fellow.
  • Move into technical management roles leading failure analysis teams or quality organizations.
  • Expand expertise into broader reliability engineering, product development, or advanced packaging domains.
  • Perform root cause failure analysis on ASIC products, including reliability test failures and field returns.
  • Develop and implement standard failure analysis processes using various techniques like cross-section, X-ray, CSAM, FIB, SEM, and TEM.
  • Collaborate with product test, design, quality, assembly, and foundry engineering teams to identify and characterize faults.
  • Document and report results to management and act as a technical resource for failure analysis questions.
  • Deep expertise in semiconductor failure analysis techniques and equipment.
  • Strong understanding of root cause analysis and fault isolation methods using ATE, Scan/ATPG, MBIST.
  • Ability to interpret FA results and provide clear guidance on failure causes.
  • Excellent communication and collaboration skills for cross-functional teamwork.

申请策略

  • Tailor your resume to match the specific FA techniques mentioned in the job description.
  • Highlight any experience with supplier management or driving physical failure analysis with external vendors.
  • Research Cisco's quality and reliability practices and their focus on AI-era infrastructure.
  • Highlight years of hands-on experience in semiconductor failure analysis and specific FA techniques used.
  • Emphasize successful root cause analysis projects that led to corrective actions and yield improvements.
  • Showcase knowledge of fault isolation tools like ATE, Scan/ATPG, MBIST, and dynamic FA setups (SIL, LSM).
  • Include experience working with cross-functional teams and suppliers in semiconductor environments.
  • Familiarize yourself with JEDEC reliability standards and advanced packaging technologies.

面试指南

  • Use the STAR method: Situation, Task, Action, Result. Focus on your specific role and the impact of your actions.
  • Emphasize your systematic approach to failure analysis, from initial characterization to root cause confirmation.
  • Highlight collaboration with cross-functional teams and how you communicated findings to non-experts.
  • Describe a challenging failure analysis you performed from start to finish. What techniques did you use and how did you isolate the root cause?
  • How would you approach a new failure event where the root cause is not immediately apparent?
  • Explain how you would use ATE or Scan/ATPG to isolate a device-level fault.
  • How do you prioritize and manage multiple failure analysis requests with tight deadlines?
  • Describe your experience with advanced packaging failure analysis. What specific challenges have you encountered?

职位点评

72
综合评分

A senior technical role at a global leader, focused on ASIC failure analysis with advanced FA techniques, offering strong growth and compensation but limited work location flexibility.

从薪资福利、成长空间、工作节奏和岗位方向综合评估,方便横向比较。

更适合这类人
This role is best suited for professionals who are highly motivated by technical depth and continuous skill development, and are comfortable with a highly specialized, lab-centric working environment.
表现最好
成长发展
相对薄弱
使命价值
薪资福利75
成长发展80
工作生活65
使命价值60

薪资福利

75中等

Cisco is a leading global company that offers competitive compensation, and this senior role is likely well-paid. However, the JD does not disclose specific salary or benefits, so there is some uncertainty.

薪资信号未披露(AI估算:40K-60K/月)

成长发展

80较高

This role provides deep technical growth in specialized failure analysis techniques and collaboration with multiple engineering teams, making it a strong fit for those seeking expertise.

技术前沿前沿/新兴技术
技术栈Failure Analysis、ASIC、Cross Section、X-ray、CSAM、TDR、FIB、SEM、TEM、IR/EMMI/OBIRCH、SIL、LSM、ATE、Scan/ATPG、MBIST
业务类型ambiguous

工作生活

65中等

The work is lab-based and likely requires on-site presence, but specific work-life balance policies are not mentioned in the JD. Cisco generally has a good work culture, but this role may involve hands-on lab time.

工作模式仅现场办公
办公地点未明确
加班情况未提及(无法判断)

使命价值

60中等

The semiconductor industry is growing, and this role contributes to product quality and reliability, which has a moderate impact. The job is more technical than socially impactful.

行业发展高速增长赛道
社会影响中性/一般
创新程度积极采用新技术
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