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Senior Staff Manager, Physical Design
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Senior Staff Manager, Physical Design

发布于 大约 3 小时前

中层管理(经理/总监)

Hsinchu City, Taiwan
高级经验
全职员工
仅现场办公
本科
芯片设计
Asic
Clock Tree Synthesis
Eda Tools
Physical Design
Power Analysis
Soc
Team Leadership
Rtl To Gdsii

AI 估算 · 40k–60k

Based on senior management level and semiconductor industry salary benchmarks in Hsinchu area.

职位详情

关于这个职位

Marvell is seeking a Senior Manager of Physical Design to lead project-level physical design execution and support team growth in Hsinchu, Taiwan. You will manage a team of engineers, drive RTL to GDSII implementation for complex SoCs, and collaborate with global teams to deliver high-quality semiconductor solutions. This role offers the opportunity to work on cutting-edge process nodes and build a high-performing team.

最低要求

· Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or a related field.

· 10+ years of experience in ASIC physical design and SoC implementation.
· Experience leading a team of engineers and driving project-level physical design execution.
· Proven track record of delivering successful SoC or subsystem tapeouts.
· Good understanding of physical design methodologies, flows, and advanced process technologies.
· Proficiency with ASIC design flows and commonly used EDA tools.
· Strong technical problem-solving skills and effective communication with cross-functional teams.

工作职责

· Lead physical design execution for assigned blocks, subsystems, or projects, managing a team of physical design engineers.

· Support hiring, onboarding, and day-to-day team management, including performance feedback and career development.
· Drive RTL to GDSII implementation, including synthesis, floorplanning, place and route, clock tree synthesis, timing closure, power/signal integrity analysis, and physical verification.
· Ensure on-time, high-quality delivery by tracking schedules, identifying risks early, and executing mitigation plans.
· Follow and apply established physical design methodologies, flows, and best practices, while providing feedback for continuous improvement.
· Work closely with cross-functional teams (architecture, RTL, CAD, DFT, timing) to address design and implementation challenges.
· Collaborate with global PD teams to ensure alignment on execution plans and technical decisions.
· Escalate risks, issues, and resource gaps to leadership in a timely manner.
· Provide technical guidance and hands-on support to the team to ensure strong execution and quality.
· Mentor engineers and contribute to building a high-performing and collaborative team environment.

优先资格

· Experience applying and improving physical design methodologies and flows at the project or block level.

· Exposure to automation and data-driven design optimization techniques.
· Familiarity with AI/ML-assisted features in modern physical design tools.
· Experience collaborating with cross-functional teams in a multi-site or global development environment.

AI 洞察

优缺点分析

优点

  • Lead cutting-edge semiconductor designs for AI, cloud, and infrastructure markets.
  • Work with a global team at a respected industry leader (Marvell).
  • Opportunity to shape team culture and influence technical direction.
  • Competitive compensation and benefits package.
  • High pressure to meet aggressive tapeout schedules with zero defects.
  • Managing cross-site collaboration across time zones.
  • Requires deep technical expertise and continuous learning of new process technologies.
  • Experienced physical design engineers with 10+ years of experience who are ready to take on a managerial role and thrive in a fast-paced, technically demanding environment.

缺点 / 挑战

暂无明显挑战项

角色解读

  • Progress to Director of Physical Design or broader ASIC engineering leadership.
  • Expand into methodology development for next-generation process technologies.
  • Transition to senior technical leadership roles (e.g., Principal Engineer, Fellow).
  • Lead a team of physical design engineers to execute RTL-to-GDSII implementation for complex SoCs.
  • Drive floorplanning, placement, routing, clock tree synthesis, timing closure, and physical verification.
  • Collaborate with cross-functional teams (architecture, RTL, CAD, DFT) to resolve design challenges.
  • Manage project schedules, risks, and deliverables while mentoring team members.
  • Deep expertise in ASIC physical design and advanced process nodes (e.g., 7nm, 5nm).
  • Proficiency with industry-standard EDA tools (Synopsys, Cadence).
  • Strong leadership and project management experience.
  • Excellent problem-solving and cross-team communication skills.

申请策略

  • Tailor your resume to reflect strong technical leadership and hands-on physical design expertise.
  • Prepare examples of how you resolved complex timing or power issues under tight schedules.
  • Emphasize successful tapeout experiences and specific process nodes (e.g., 7nm, 5nm).
  • Highlight leadership roles: team size, project scope, and mentoring examples.
  • Quantify PPA improvements or schedule achievements.
  • Showcase familiarity with EDA tool flows and automation/scripting skills.
  • If not already skilled, learn advanced EDA tool scripting (Tcl, Python) for flow automation.
  • Stay updated on AI/ML-assisted physical design techniques (e.g., Synopsys DSO.ai).

面试指南

  • Use STAR method (Situation, Task, Action, Result) for behavioral questions.
  • For technical questions, explain the problem, your analysis, the solution, and the impact.
  • Demonstrate leadership by highlighting how you guided the team and made decisions.
  • Describe a challenging tapeout you led and how you ensured on-time delivery.
  • How do you approach floorplanning for a complex SoC?
  • How do you manage cross-site team collaboration and communication?
  • What is your experience with advanced process nodes (e.g., 5nm, 3nm)?
  • How have you improved physical design methodologies in your previous roles?

职位点评

72
综合评分

High-impact management role in cutting-edge semiconductor design with strong growth potential but limited work flexibility.

从薪资福利、成长空间、工作节奏和岗位方向综合评估，方便横向比较。

更适合这类人
Candidates prioritizing career growth, technical challenges, and compensation, and who are comfortable with an on-site, demanding work environment.
表现最好
成长发展
相对薄弱
工作生活
薪资福利80
成长发展85
工作生活50
使命价值60

薪资福利

80较高

Senior management role with competitive compensation and benefits, including potential equity. Marvell is a well-established company, so salary and stability are strong.

薪资信号面议 (40K-60K/月)
福利待遇competitive compensation、great benefits

成长发展

85较高

Opportunity to lead teams, refine methodologies, and work on advanced process nodes. Marvell offers a growth-oriented environment with mentorship and career development.

技术前沿前沿/新兴技术
技术栈Physical Design、ASIC、Advanced Process Nodes、AI/ML-assisted features
成长机会career development、mentor、team development
业务类型profit_center

工作生活

50较低

On-site role in Hsinchu (science park) with no mention of remote flexibility. Semiconductor industry often involves long hours during tapeout, but no explicit overtime signals.

工作模式仅现场办公
办公地点科技园/产业园
加班情况未提及（无法判断）

使命价值

60中等

Marvell's focus on data infrastructure and AI contributes to meaningful technology, but the role is more execution-oriented than mission-driven.

行业发展高速增长赛道
社会影响正向社会影响力较高
使命信号data infrastructure、transformative potential
创新程度积极采用新技术

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