Sr. Digital Verification Engineer (Taipei)
发布于 大约 15 小时前普通员工/个人贡献者
AI 估算 · 25k–45k
Senior digital verification engineer in semiconductor industry, Taiwan market rate for 5-8 years experience is approximately 3.5
职位详情
关于这个职位
This position is for a Senior Digital Verification Engineer at Monolithic Power Systems (MPS), a leading semiconductor company. You will verify digital and mixed-signal ICs for power management and signal management products, using UVM and SystemVerilog. This role involves developing verification plans, creating verification environments, and collaborating with design teams.
最低要求
MS in Electrical Engineering with 5-8 years of experience in verification of digital ASIC design.
工作职责
Generation of verification plans based on design requirements and product datasheets of digital / mixed- signal IC’s.
优先资格
Knowledge/Experience with the following is a plus:
AI 洞察
优缺点分析
优点
- MPS is a fast-growing company in the semiconductor industry, offering job stability and growth.
- Work with cutting-edge technologies in power management and mixed-signal ICs.
- Highly specialized role with strong demand for verification skills, providing career security.
- Opportunity to develop deep expertise in verification methodologies like UVM and formal verification.
- High complexity of verification tasks requires meticulous attention to detail and debugging skills.
- Tight project schedules may lead to periods of intense work and overtime.
- Requires continuous learning to keep up with evolving tools and methodologies.
- This role is ideal for experienced verification engineers who enjoy technical depth, problem-solving, and working on advanced chip designs in a collaborative environment.
缺点 / 挑战
暂无明显挑战项
角色解读
- Progress to Staff or Principal Verification Engineer, leading larger verification efforts.
- Move into design roles (front-end or back-end) with deeper RTL knowledge.
- Transition into architecture or project management roles within semiconductor companies.
- Develop verification plans and testbenches for digital and mixed-signal ICs using UVM and SystemVerilog.
- Work closely with digital and analog designers to create system-level and behavioral models.
- Run simulations, debug failures, and analyze coverage metrics to ensure design quality.
- Automate verification flows and develop reusable verification IP.
- Strong expertise in SystemVerilog, UVM, and digital verification methodologies.
- Understanding of ASIC design flow, digital design techniques, and mixed-signal verification.
- Proficiency in scripting languages like TCL, Python, or C/C++ for automation.
- Excellent communication and teamwork skills for cross-functional collaboration.
申请策略
- Tailor your resume to match the specific requirements: ASIC DV, UVM, and scripting.
- Prepare to discuss a challenging verification project you led, including how you solved coverage gaps.
- Emphasize hands-on experience with UVM and SystemVerilog in complex verification environments.
- Showcase your ability to create verification plans and achieve high coverage metrics.
- List specific scripting skills (TCL, Python, Perl) and any automation frameworks you built.
- Highlight any domain knowledge in power management or mixed-signal verification.
- Brush up on advanced UVM concepts like sequences, factories, and analysis ports.
- Gain familiarity with formal verification tools (e.g., Jasper, Synopsys VC Formal) for completeness.
面试指南
- Use the STAR method (Situation, Task, Action, Result) for behavioral questions.
- For technical questions, explain your thought process step-by-step, connecting theory to practical experience.
- Show enthusiasm for verification and emphasize quality and efficiency.
- How do you plan verification for a mixed-signal block?
- Describe a bug you found late in the verification cycle and how you prevented it.
- Explain the UVM factory pattern and when you would override a component.
- How do you measure functional coverage and what steps do you take to close coverage holes?
- Tell me about your experience with a scripting language for automation in verification.
职位点评
Senior digital verification role in a stable semiconductor company, strong technical depth but limited WLB flexibility.
从薪资福利、成长空间、工作节奏和岗位方向综合评估，方便横向比较。
薪资福利
Senior position in semiconductor industry offers competitive salary and benefits. Taiwan market for experienced verification engineers is stable, but cost of living in Taipei is high.
成长发展
Role involves modern verification methodologies (UVM, SystemVerilog) and scripting, with opportunities to work on advanced mixed-signal chips. Growth potential within a large tech company.
工作生活
On-site work in Taipei office, no remote flexibility mentioned. Semiconductor industry can have intense deadlines, potentially leading to overtime.
使命价值
MPS emphasizes sustainability and innovation in power semiconductors, contributing to energy efficiency. However, the role is technical and not directly mission-driven.