Design Verification Engineer
发布于 大约 17 小时前普通员工/个人贡献者
值不值得投
综合评分 73
Technical verification role at a leading chip company, with strong development opportunities but standard office-based work.
从薪资福利、成长空间、工作节奏和岗位方向综合评估，方便横向比较。
薪资怎么样
28K
比芯片设计中位数低
发布情况
新岗位 · 今天发布
公司情况
这家公司招聘很活跃
约 400 个在招 · 其中芯片设计 约 190 个
市场机会
选择面较广
芯片设计 · 约 790 个在招
职位详情
关于这个职位
This role is responsible for developing and implementing verification plans for MediaTek's smartphone, TV, and ASIC product lines. You will build integrated simulation and verification environments, perform big data analysis to improve efficiency, and verify complex functions like bus fabric, EMI, and low power features. The position requires leveraging the latest EDA tools to ensure robust design verification in deep sub-micron process nodes.
最低要求
Have a good command of Verilog / System Verilog / C++ / Perl
工作职责
As deep sub-micron process requires longer research cycle and higher manufacture cost, DV(design verification) has become an inevitable part of design group in Mediatek chip development flow. CDG DV is in charge of development and implementation of smart phone, TV, and ASIC product line verification plan. It included: integrated simulation/verification env development, big data analysis and efficiency improvement, bus fabric / EMI (External memory interface ) / Low power functions verification plan and implementation Need to build up verification plan/bench and continuously improve methodology, and you will understand both detail scenario and global view of cell phone/ASIC operating schemes Need to leverage the latest EDA tool and concept to accomplish the verification plan
优先资格
ARM Based SOC verification experience is a plus.
AI 洞察
优缺点分析
优点
- Work on cutting-edge deep sub-micron chip design verification with significant technical impact.
- Join a leading global semiconductor company (Mediatek) with a strong product portfolio.
- Access to advanced EDA tools and opportunities for skill development in verification methodologies.
- Rapid technology evolution requires continuous learning and adaptation to new tools and standards.
- Complex verification tasks may involve tight deadlines and high attention to detail.
- Collaboration with cross-functional teams can present coordination challenges in large-scale projects.
- Engineers passionate about semiconductor design verification, who thrive on technical challenges, and prefer roles with high precision and teamwork.
缺点 / 挑战
暂无明显挑战项
角色解读
- Progress to senior verification engineer or verification architect roles with deeper technical expertise.
- Transition into chip design management or methodology leadership positions.
- Specialize in emerging verification technologies or cross-functional roles in product development.
- Develop and implement verification plans for smartphone, TV, and ASIC product lines at MediaTek.
- Create integrated simulation and verification environments to ensure design robustness.
- Utilize big data analysis to improve verification efficiency and methodology.
- Verify critical functions such as bus fabric, external memory interfaces, and low power features.
- Proficiency in hardware description languages like Verilog/SystemVerilog and programming skills in C++/Perl.
- Expertise in UVM (Universal Verification Methodology) and formal verification techniques.
- Experience with ARM-based SOC verification and chip-level verification is advantageous.
- Strong organizational skills, attention to detail, and teamwork capabilities.
申请策略
- Research Mediatek's product lines (smartphones, TVs, ASICs) to tailor your application and show industry awareness.
- Prepare to discuss specific verification scenarios and how you leveraged EDA tools to solve problems.
- Highlight hands-on experience with Verilog/SystemVerilog, UVM, and formal verification in past projects.
- Detail any involvement in ARM SOC or chip-level verification tasks to demonstrate relevant expertise.
- Emphasize organizational skills and teamwork through examples of collaborative projects or methodology improvements.
- Deepen knowledge of UVM advanced features and formal verification tools to align with job requirements.
- Explore ARM architecture specifics and SOC integration challenges to prepare for potential interview questions.
- Practice big data analysis techniques relevant to verification efficiency improvements.
面试指南
- Use the STAR method (Situation, Task, Action, Result) to structure responses around project examples.
- Focus on technical depth by detailing specific tools, methodologies, and outcomes.
- Highlight soft skills like organization and teamwork by referencing real-world collaboration experiences.
- Can you explain your experience with UVM and how you've applied it in verification projects?
- Describe a challenging verification scenario you've handled, such as verifying bus fabric or low power functions.
- How do you approach building an efficient verification environment for complex SOCs?
- What techniques do you use for big data analysis to improve verification productivity?
- How do you ensure teamwork and collaboration in a multidisciplinary verification team?
职位点评
薪资福利
The position likely offers competitive compensation given the technical specialization and company's market position, though specific salary details are not disclosed in the JD.
成长发展
The role provides strong opportunities for skill growth in advanced verification methodologies and cutting-edge chip design, with potential for career progression in a leading tech company.
工作生活
The work requires on-site presence in Hsinchu, with no mention of flexible work arrangements, suggesting a standard office-based schedule.
使命价值
The role contributes to the development of advanced semiconductor technologies in a high-growth industry, offering impact through innovation in chip design verification.