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SoC Physical Design Engineer, Sr Staff

SoC Physical Design Engineer, Sr Staff

发布于 大约 3 小时前

普通员工/个人贡献者

Taipei, Taiwan
专家级经验
全职员工
仅现场办公
本科
硬件工程师
Apr
Low Power
Physical Design
Pv
Soc
Sta
Upf
Ir/Em
Synopsys Eda

AI 估算 · 45k–80k

Senior physical design engineer at a leading EDA company in Taiwan, competitive semiconductor market.

职位详情

关于这个职位

As a Senior Staff SoC Physical Design Engineer at Synopsys, you will collaborate with customer IC design teams to achieve successful tape-outs using Synopsys EDA tools, focusing on physical implementation, timing closure, IR/EM, and physical verification. This role requires deep expertise and offers the opportunity to work on cutting-edge chip designs.

最低要求

+ years of industry experience in SOC engineering

Expertise in physical implementation and timing closure
Experience with STA and IR/EM
Strong verbal and written English communication skills
Excellent customer interfacing abilities
A collaborative team player with a proactive approach
A sophisticated professional with advanced knowledge and wide-ranging experience
An effective communicator capable of interacting with diverse stakeholders
Highly organized and able to manage complex issues with minimal supervision
A problem solver with a keen eye for detail and quality

工作职责

Collaborating with other FE and BE engineers or customer engineers to assist in successful tape-outs from RTL to GDS or from Netlist to GDS using Synopsys EDA tools

Focusing on areas such as physical implementation, IR/EM, physcial verification and timing closure.
Working as a member of the customer's IC design team, providing immediate impact on their current project while transferring valuable knowledge for future projects
Interacting regularly with customers to identify and eliminate barriers to project success
Planning and managing the delivery of your own project-related tasks
Leveraging the entire Synopsys team to ensure project success and providing feedback to R&D/AE on suggested tool enhancements or issues
Working with or as a Project Leader to develop technical proposals, working through the project life cycle, and producing consistently high-quality technical solutions.

优先资格

Knowledge of UPF and low power techniques

AI 洞察

优缺点分析

优点

  • Work at a leading EDA company with advanced technology and strong industry reputation.
  • Opportunity to collaborate with diverse customer teams and learn best practices.
  • High compensation potential due to seniority and specialized skills.
  • Contribute to cutting-edge chip designs enabling AI and Pervasive Intelligence.
  • High responsibility and pressure to ensure successful tape-outs within deadlines.
  • Frequent customer interaction may require travel or flexible scheduling.
  • Need to continuously update skills with evolving process nodes and tool features.
  • This role is ideal for experienced physical design engineers who enjoy technical depth and customer engagement and seek a stable yet challenging position.

缺点 / 挑战

暂无明显挑战项

角色解读

  • Progress to technical expert or principal engineer roles, leading larger tape-outs or multiple projects.
  • Move into customer-facing consulting roles, developing technical proposals and influencing tool roadmap.
  • Transition to R&D positions, providing feedback to improve Synopsys tools.
  • Collaborate with front-end and back-end engineers to ensure successful tape-outs from RTL to GDS or Netlist to GDS using Synopsys tools.
  • Focus on physical implementation, IR/EM, timing closure, and physical verification for complex SoC designs.
  • Interact directly with customers to identify and remove project barriers, acting as a technical consultant.
  • Plan and manage project tasks, potentially leading technical proposals and working through the project lifecycle.
  • Deep expertise in physical design and timing closure, with 10+ years of SOC engineering experience.
  • Proficiency in Synopsys EDA tools including APR, STA, and physical verification.
  • Strong English communication and customer interfacing skills to work effectively with diverse teams.
  • Knowledge of low power techniques and UPF is a plus.

申请策略

  • Research Synopsys' product portfolio and recent innovations to show genuine interest.
  • Be prepared to discuss specific examples of how you've driven tape-out success and overcome barriers.
  • Highlight your 10+ years of SOC physical design experience with specific tape-out successes.
  • Emphasize expertise in timing closure, IR/EM, and physical verification, with named tools.
  • Showcase customer-facing project examples where you solved complex design issues.
  • Include any experience with UPF and low power techniques.
  • Brush up on latest Synopsys tools and flow, such as Fusion Compiler or IC Compiler II.
  • Deepen understanding of advanced process node challenges and design closure techniques.

面试指南

  • Use the STAR method (Situation, Task, Action, Result) to structure behavioral answers.
  • For technical questions, demonstrate a structured problem-solving approach: define the issue, analyze root cause, propose solutions, and validate results.
  • For customer-facing scenarios, emphasize communication, empathy, and alignment with business goals.
  • Describe a complex timing closure challenge you faced and how you resolved it.
  • How do you prioritize tasks when managing multiple tape-out projects?
  • Explain your approach to working with customers who have conflicting requirements.
  • What is your experience with low power design techniques and UPF?
  • How do you stay updated with evolving EDA tools and methodologies?

职位点评

70
综合评分

Senior physical design role at Synopsys, strong technical growth, unclear work-life balance.

从薪资福利、成长空间、工作节奏和岗位方向综合评估,方便横向比较。

更适合这类人
This role is best suited for candidates who value technical excellence and career progression, and are comfortable with a demanding but rewarding environment.
表现最好
成长发展
相对薄弱
工作生活
薪资福利65
成长发展85
工作生活55
使命价值75

薪资福利

65中等

The role likely offers competitive compensation for a senior engineer, but salary specifics are not disclosed in the JD.

薪资信号未披露(AI估算:45K-80K/月)

成长发展

85较高

The role provides deep technical challenges and access to advanced EDA tools, fostering significant skill development.

技术前沿前沿/新兴技术
技术栈Physical Design、Timing Closure、STA、IR/EM、UPF、Low Power、Synopsys EDA、APR、PV
业务类型ambiguous

工作生活

55较低

No explicit work-life balance information is provided; the role may involve on-site work and customer interaction.

工作模式未明确
办公地点未明确
加班情况未提及(无法判断)

使命价值

75中等

The work contributes to the era of pervasive intelligence and continuous innovation, offering a sense of purpose.

行业发展高速增长赛道
社会影响中性/一般
使命信号innovations、continuous technological innovation
创新程度积极采用新技术
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