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Application Engineering, Staff Engineer - Physical Verification (Runset Development)

Application Engineering, Staff Engineer - Physical Verification (Runset Development)

发布于 大约 3 小时前

普通员工/个人贡献者

Hsinchu, Taiwan
高级经验
全职员工
仅现场办公
本科
芯片设计
Drc
Lvs
Pegasus
Tcl
Cmos Layout
Ic Validator

AI 估算 · 45k–65k

资深EDA物理验证工程师,技术门槛高,市场需求稳定,薪资具备竞争力。

职位详情

关于这个职位

You will develop and validate DRC, LVS, and Fill runsets for Synopsys IC Validator, collaborating with top foundries to handle advanced node physical verification challenges. You will automate processes with scripting languages, support customers, and mentor younger engineers, making this a great role for experienced PV specialists.

最低要求

B.Tech, M.Tech, or MS in Electronics, VLSI, or related field.

years of hands-on experience in the Physical Verification (PV) domain.
Advanced proficiency with EDA tools such as IC Validator, Calibre, Pegasus, and PVS.
Strong scripting skills in Perl, Tcl, and Python for automation and rule deck development.
Deep understanding of CMOS layout, ASIC design flows, and foundry process requirements.
Experience in writing and debugging DRC, LVS, ERC, and DFM rule decks.
Exposure to competitive EDA tools and awareness of their strengths and limitations.

工作职责

Developing and validating DRC, LVS, and Fill runsets (rule deck files) for the Synopsys IC Validator tool, targeting state-of-the-art semiconductor technologies.

Collaborating closely with leading foundries to understand process requirements and deliver high-quality PV runsets for advanced nodes.
Automating qualification processes for IC Validator runsets using scripting languages such as Perl, Tcl, and Python.
Troubleshooting and resolving complex layout verification issues, including LVS discrepancies, DRC violations, and DFM challenges.
Interfacing directly with customers and FAEs to gather requirements, provide technical support, and ensure successful deployment of PV solutions.
Mentoring junior team members, sharing best practices, and contributing to a knowledge-sharing culture within the team.
Staying up-to-date with the latest EDA tool advancements, competitive products, and foundry process innovations to maintain Synopsys' technical edge.

AI 洞察

优缺点分析

优点

  • Work at the forefront of semiconductor technology with leading foundries and advanced process nodes.
  • High value skill set in EDA and physical verification, with strong industry demand and stability.
  • Opportunity to learn and use a wide range of industry-standard tools and scripting languages.
  • Collaborative team environment with mentoring and knowledge sharing, enhancing professional growth.
  • Physical verification for advanced nodes is highly complex and requires meticulous attention to detail.
  • Frequent interaction with customers and foundries can be demanding, requiring strong communication skills.
  • Keeping up with rapid process technology changes and continuous learning is essential.
  • This role is ideal for experienced engineers passionate about semiconductor design and EDA tools, who enjoy problem-solving and collaborating with global teams.

缺点 / 挑战

暂无明显挑战项

角色解读

  • Advance to senior technical leadership roles, leading complex runset development projects and driving innovation in EDA verification.
  • Transition into broader chip design or EDA tool development positions, leveraging deep domain knowledge.
  • Grow as a mentor and team lead, guiding larger teams and influencing industry standards in physical verification.
  • Develop and validate physical verification rule decks (DRC/LVS/Fill) for advanced semiconductor nodes using Synopsys IC Validator.
  • Collaborate with foundries to understand process design rules and translate them into efficient runset configurations.
  • Automate runset qualification processes by writing scripts in Perl/Tcl/Python, reducing manual errors and improving throughput.
  • Provide technical support to customers and FAEs, troubleshoot complex verification issues, and mentor junior engineers.
  • Deep expertise in physical verification methodologies, including DRC, LVS, ERC, and DFM rules.
  • Strong scripting and automation skills in Perl, Tcl, and Python, essential for runset development and debugging.
  • Hands-on experience with EDA tools like IC Validator, Calibre, Pegasus, and understanding of their strengths.
  • Solid understanding of CMOS layouts, ASIC design flows, and foundry process requirements.

申请策略

  • Demonstrate genuine interest in EDA and physical verification by sharing knowledge on forums or writing technical blogs.
  • Prepare to discuss specific examples of resolving difficult layout verification problems and how you interacted with customers.
  • Highlight years of experience in Physical Verification and specific projects involved in DRC/LVS runset development.
  • Showcase scripting skills with examples of automation in Perl/Tcl/Python, emphasizing efficiency improvements.
  • Mention familiarity with multiple EDA tools, especially IC Validator, Calibre, and Pegasus.
  • Emphasize any experience with foundry process nodes and DFM challenges.
  • Strengthen Python scripting, particularly using libraries for data analysis and automation.
  • Stay updated with latest IC Validator features and compare with competitor tools through online resources or training.

面试指南

  • Use the STAR method (Situation, Task, Action, Result) when describing past experiences, emphasizing technical depth and measurable outcomes.
  • Show a structured approach to debugging: reproduce, isolate, analyze, fix, and validate.
  • Highlight collaboration and communication skills when discussing interactions with customers or cross-functional teams.
  • Describe your experience developing DRC/LVS runsets for advanced nodes. What challenges did you face and how did you solve them?
  • How do you ensure the quality and accuracy of a rule deck? What automation have you implemented?
  • Explain a time you collaborated with a foundry or customer to resolve a physical verification issue.
  • How do you stay current with evolving process technologies and EDA tool updates?
  • Walk me through your scripting approach for automating runset qualification. What are some best practices?

职位点评

67
综合评分

A senior physical verification engineering role at a top EDA company, offering cutting-edge technical work in Taiwan with a standard on-site setup and strong growth opportunities.

从薪资福利、成长空间、工作节奏和岗位方向综合评估,方便横向比较。

更适合这类人
This role is best suited for engineers motivated by technical challenges, skill growth, and working with advanced semiconductor technologies, rather than those prioritizing flexible work arrangements.
表现最好
成长发展
相对薄弱
工作生活
薪资福利70
成长发展80
工作生活50
使命价值60

薪资福利

70中等

The position offers a competitive compensation package with comprehensive benefits, though exact salary is disclosed only during recruitment.

薪资信号未披露(AI估算:45K-65K/月)

成长发展

80较高

The role provides excellent opportunities to work with cutting-edge semiconductor technologies and professional growth through mentoring and continuous learning.

技术前沿前沿/新兴技术
技术栈IC Validator、Calibre、Pegasus、DRC、LVS、DFM、Perl、Tcl、Python
业务类型ambiguous

工作生活

50较低

The job requires on-site presence in Hsinchu, Taiwan, with no explicit work-life balance statements, indicating a standard on-site engineering role.

工作模式仅现场办公
办公地点未明确
加班情况未提及(无法判断)

使命价值

60中等

The role contributes to advancing chip design and enabling pervasive intelligence, but social impact is indirect and industry is mature.

行业发展稳定成熟行业
社会影响中性/一般
使命信号transform the future
创新程度积极采用新技术
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