博通
ASIC Physical Design Engineer
ASIC Physical Design Engineer
发布于 大约 8 小时前普通员工/个人贡献者
上海市
中级经验
全职员工
仅现场办公
硕士
硬件工程
ASIC
STA
DRC
LVS
TCL
DFT
VLSI
Physical Design
16Nm
AI 估算 · 25k–40k
博通作为跨国EDA大厂，薪资有竞争力；ASIC物理设计技能稀缺，先进工艺节点加成，月薪在行业中上水平。
职位详情
关于这个职位
这是博通公司的一个ASIC物理设计工程师职位，你将参与最先进的28nm/16nm/7nm工艺芯片设计，负责从RTL分析到物理实现、时序验证的全流程工作
职位要求具备扎实的VLSI背景和独立处理模块的能力，适合追求技术深度和先进工艺的芯片工程师
最低要求
Candidates should have good understanding about ASIC design flow and solid VLSI background.
Candidates should be able to handle block implementation/top level task independently.
Tapeout experience in 28nm and blow process design.
Candidates should have strong communications and problem solving skills.
工作职责
RTL analysis, synthesis, design optimization, timing verification, simulation, test insertion, physical design, vector generation, and post-prototype test support.
Full Chip Synthesis and STA: background on full chip synthesis flow (DC, DCT, DCG) for 16nm/7nm design tape out; experience running full chip STA and constraint clean up flow.
Physical Design Implementation: background in floor planning, placement, design closure, and DRC & LVS skills.
优先资格
DFT insertion
Power/IVD analysis
DRC/LVS
Good at Perl/Tcl
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匹配度报告
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