Watch Jobs
Cisco logo
思科
ASIC Engineer
立即应聘

ASIC Engineer

发布于 大约 14 小时前

普通员工/个人贡献者

Hsinchu, Hsinchu City, Taiwan
高级经验
全职员工
仅现场办公
不限
芯片设计
Asic
Debugging
Eda
Physical Design

AI 估算 · 35k–50k

Experienced ASIC engineer in Hsinchu, competitive salary at Cisco, but specifics undisclosed.

职位详情

关于这个职位

This ASIC Engineer role at Cisco involves defining, designing, and verifying ASIC subsystems for a range of Cisco platforms. You will contribute to a multidisciplinary team to achieve power, performance, and area goals, and help define design methodologies for complex developments.

最低要求

Typically: Bachelors + 7 years of related experience, or Masters + 4 years of related experience, or PhD + 1 year of related experience

工作职责

Drives the definition, architecture and design of high performance ASICs

Owns complex or multiple functional areas
Develops reusable code for future projects
Creates re-usable code
Debugs at ASIC, SW, HW level
Works with ASIC and Apps, with limited external scope
Leads design work by solving block level issues and participates in chip level issue resolution
Drives reviews and recognizes areas of architectural concerns
Defines new verification methodologies
Helps in lab bring up
Leads code reviews at platform level
Defines methodologies of execution for analog/mixed signal products
Collaborates with the mixed-signal team and system teams to help define and specify the requirements
Responsible for testing high accuracy analog designs, and helping to suppo
Develops and deploys PD EDA flows
Owns physical design of highly complex blocks
Identifies, designs and implements power and signaling solutions

优先资格

Varies based on the team and business needs | Preferred Qualifications are desired education, experience, and skills that are in addition to Minimum Qualifications

AI 洞察

优缺点分析

优点

  • Work on cutting-edge ASICs for a global networking leader with proven impact.
  • Significant technical ownership and the chance to drive complex designs.
  • Multidisciplinary team environment fosters learning in mixed-signal, EDA, and verification.
  • Competitive compensation and benefits typical of a multinational corporation.
  • Complex debugging across multiple layers (ASIC, SW, HW) can be demanding.
  • High expectations for power, performance, and area targets require meticulous execution.
  • Requires extensive experience and self-direction to handle multiple functional areas.
  • Experienced ASIC engineers who enjoy deep technical challenges, ownership, and collaboration in a structured, large-company environment.

缺点 / 挑战

暂无明显挑战项

角色解读

  • Advance to senior ASIC architect or technical lead with broader chip-level influence.
  • Opportunity to shape Cisco's next-gen networking and AI infrastructure solutions.
  • Gain versatile expertise across mixed-signal, verification, and physical design domains.
  • Define and architect high-performance ASICs for Cisco platforms, driving complex functional areas.
  • Own debug efforts at ASIC, software, and hardware levels, and lead design reviews.
  • Develop reusable code and create new verification methodologies for analog/mixed-signal products.
  • Collaborate with mixed-signal and system teams to specify requirements and support lab bring-up.
  • Strong ASIC design and verification skills, including RTL and verification methodologies.
  • Experience with physical design, EDA flows, and power/signaling solutions.
  • Proficiency in debugging across ASIC, software, and hardware boundaries.
  • Typically requires Bachelors +7 years, Masters +4 years, or PhD +1 year of related experience.

申请策略

  • Research Cisco's AI-era infrastructure strategy and align your experience with their innovation areas.
  • Tailor your resume to the specific ASIC team's focus, whether mixed-signal, physical design, or verification.
  • Highlight ASIC design and verification projects with quantifiable outcomes (e.g., PPA improvements).
  • Emphasize experience with physical design, EDA flows, and mixed-signal collaboration.
  • Showcase debug examples across ASIC, software, and hardware, including resolution impact.
  • Mention reusable code or methodologies you have developed and deployed.
  • Brush up on modern verification methodologies like UVM and formal verification.
  • Gain familiarity with EDA tools and scripting (Python, Tcl) for flow automation.

面试指南

  • Use the STAR method: Situation, Task, Action, Result.
  • Focus on technical problem-solving and cross-functional collaboration.
  • Quantify achievements with metrics like PPA improvements, bug reduction, or time saved.
  • Describe a complex ASIC design or verification project you led. What was your approach?
  • How do you handle block-level issues and escalate to chip-level resolution?
  • What strategies have you used to optimize power, performance, and area (PPA)?
  • Tell us about a methodology you defined for verification or physical design.
  • How do you collaborate with mixed-signal and system teams to gather requirements?

职位点评

65
综合评分

Senior ASIC engineer role at Cisco with strong technical depth, solid pay, but limited work flexibility.

从薪资福利、成长空间、工作节奏和岗位方向综合评估，方便横向比较。

更适合这类人
Candidates motivated by technical growth and ownership, with tolerance for on-site work in a stable industry.
表现最好
成长发展
相对薄弱
工作生活
薪资福利65
成长发展80
工作生活50
使命价值55

薪资福利

65中等

Competitive pay at a global company, but specifics are not disclosed.

薪资信号未披露（AI估算：35K-50K/月）

成长发展

80较高

Strong technical growth in ASIC design, verification, and architecture with significant ownership.

技术前沿主流现代技术
技术栈ASIC、Verification、EDA、Physical Design、Power
业务类型ambiguous

工作生活

50较低

On-site role in Hsinchu science park, no flexibility mentioned.

工作模式未明确
办公地点科技园/产业园
加班情况未提及（无法判断）

使命价值

55较低

Stable industry with moderate social impact, Cisco's mission adds purpose.

行业发展稳定成熟行业
社会影响中性/一般
使命信号protect organizations
创新程度稳健跟随主流

思科 的其他在招职位

相似职位推荐

Watch Jobs