Sr. Associate PCB Engineer (Taipei)
发布于 1 天前普通员工/个人贡献者
AI 估算 · 18k–30k
高级PCB设计岗，AI硬件领域技能稀缺，台企/美企薪资中上，约18-30K人民币/月。
职位详情
关于这个职位
You will own the complete PCB layout process from schematic ECO to manufacturing release, working on advanced AI Server, Data Center, and Power applications. This senior role demands deep expertise in high-multilayer board design, HDI structures, and SI/PI knowledge, using Cadence Allegro as the primary tool. Join a global semiconductor leader to drive innovative power solution hardware.
最低要求
Basic communication skills in English.
工作职责
Own and manage the complete PCB layout workflow from schematic ECO to manufacturing release.
优先资格
Experience in AI Server/HVDC (800V)/Low-loss Materials/multilayer PCB designs is highly preferred.
AI 洞察
优缺点分析
优点
- Work on cutting-edge AI Server and Data Center power technologies in a high-demand industry.
- Company is a global semiconductor leader, offering strong technical platform and career stability.
- Full ownership of critical layout processes provides high visibility and professional growth.
- Opportunity to leverage deep expertise in HDI and high-layer-count PCBs, enhancing market value.
- High complexity and pressure from tight project timelines and stringent quality requirements.
- Requires continuous learning to stay current with evolving HDI, SI/PI, and high-speed design techniques.
- Role demands close cross-functional coordination, which can be challenging with distributed teams.
- This role is ideal for a seasoned PCB layout engineer who thrives on complex technical challenges and wants to make a tangible impact in next-generation power and AI hardware.
缺点 / 挑战
暂无明显挑战项
角色解读
- Progress to Principal/Senior Staff PCB Engineer, leading complex designs and mentor junior engineers.
- Expand into signal integrity (SI), power integrity (PI) co-design, or system-level architecture roles.
- Move towards technical management or cross-domain hardware system ownership within the company.
- Own the entire PCB layout lifecycle, from schematic ECO to production release, ensuring high-quality designs.
- Build and refine PCB footprint/libaries, optimize placement, routing, and stack-ups for complex multilayer boards (8–30+ layers).
- Collaborate with manufacturing partners to resolve engineering queries and ensure DFM/DFA compliance.
- Design HDI structures using blind/buried/microvia technologies for advanced AI and power applications.
- Deep expertise in Cadence Allegro PCB Designer and OrCAD Capture.
- + years of layout experience in power, analog, or mixed-signal designs.
- Strong knowledge of SI/PI, HDI design rules, stack-up planning, and PCB fabrication processes.
- English communication skills for global collaboration.
申请策略
- Research MPS's product lines and technical white papers to show genuine interest and industry awareness.
- Be prepared to discuss specific challenges you solved in previous layouts, particularly high-density and high-speed boards.
- Emphasize 8+ years of hands-on PCB layout experience, especially on 8–30 layer boards and HDI structures.
- Showcase proficiency in Cadence Allegro and OrCAD with specific project examples.
- Highlight any prior work in AI Server, high-voltage (HVDC), or low-loss materials.
- Include detailed design-for-manufacturing solutions you implemented to reduce errors or cost.
- Deepen understanding of HDI techniques, such as laser microvias and sequential lamination.
- Study signal integrity and power integrity fundamentals to speak fluently with design engineers.
面试指南
- Use the STAR method (Situation, Task, Action, Result) for behavioral questions, quantifying results when possible.
- For technical questions, explain your design process step-by-step, highlighting constraints and trade-offs.
- Demonstrate your problem-solving mindset by giving examples of how you identified and fixed manufacturing issues.
- Describe your experience with HDI PCB design and the challenges you've faced with blind/microvia routing.
- How do you approach stack-up planning to optimize SI/PI performance while ensuring manufacturability?
- Can you walk through a complex multilayer layout you completed, including how you handled DFM issues?
- How do you collaborate with hardware engineers and fabricators to resolve engineering queries?
- What is your strategy for managing layout designs with 30+ layers and high component density?
职位点评
Fast-growing semiconductor company, high-tech PCB design role, strong development opportunities but limited WLB clarity.
从薪资福利、成长空间、工作节奏和岗位方向综合评估，方便横向比较。
薪资福利
The JD does not disclose salary or benefits, but the company's strong market position and senior role imply competitive compensation. However, lacking explicit numbers makes it moderate.
成长发展
This role offers deep technical growth in cutting-edge AI Server and power electronics, with ownership of complex PCB layout processes. The company is a technology leader, providing a rich learning environment.
工作生活
Work site is in Taipei, on-site only, with no WLB signals in the JD. The high complexity and project expectations may involve overtime, though not explicitly stated.
使命价值
The work contributes to energy-efficient power solutions for AI/data center infrastructure, aligning with industry sustainability trends. The mission statement highlights innovation and sustainability, yet the direct social impact is moderate.