Watch Jobs
Renesas logo
瑞萨电子
(Sr.) Staff Package Design Engineer - MIS substrate/FC expose die （ Experienced in Power or Gan is requried )
立即应聘

(Sr.) Staff Package Design Engineer - MIS substrate/FC expose die （ Experienced in Power or Gan is requried )

发布于 大约 7 小时前

普通员工/个人贡献者

Taipei, Taiwan
专家级经验
全职员工
仅现场办公
本科
硬件工程
Doe
Flip-Chip
Gan
Osat
Power Sip
Spc
Wafer Level Packaging

AI 估算 · 40k–60k

该职位要求10年以上封装经验，技术门槛高，瑞萨为全球半导体巨头，薪资处于市场高端水平。

职位详情

关于这个职位

This role involves developing advanced packaging technologies for power SiP modules, wafer-level, and flip-chip packages at Renesas, with a focus on power and GaN applications. The engineer will collaborate with OSAT partners, run DOE to optimize processes, qualify new packages, and ensure smooth production ramp-up. This is a senior expert position requiring deep experience in power electronics packaging.

最低要求

Doctorate/Masters / Bachelor’s degree in Physics, Chemistry, Mechanical, Electrical or Materials Engineering.

>10 years of relevant experience in package development emphasizing power SiP/module, wafer level & flip-chip packaging.
Strong understanding of power SiP/modules, wafer level/flip-chip packaging methods, assembly process knowledge, qualification methods, SPC and statistical analysis software.
Strong interpersonal and communication skills.
Strong analytical and presentation skills.

工作职责

Benchmark, select and qualify suitable materials, processes and assembly subcontractors (OSAT) or contract manufacturers (CM).

Work with OSAT/CM to develop, run DOE to optimize processes, establish process spec & monitor and resolve process issues early in the production to ensure only parts with superior quality shipped to customer.
Work with Product groups and Reliability team, qualify new packages and processes within required time frame & further address internal and external customer complains working with peers of Marketing, Product groups, Quality and Operations organization to satisfy growth in businesses.
Ensure smooth transition into production & implement ramp up monitor.
Participate in packaging roadmap development & focus on execution, develop and maintain technical expertise on advances and innovations in power SiP/modules, wafer level packaging, flip chip interconnects and panel level package.
Establish & maintain package design rules.

优先资格

Knowledge of wire-bonding & multi-chip module technologies is a plus.

AI 洞察

优缺点分析

优点

  • Work on cutting-edge power semiconductor packaging technology, including GaN.
  • Opportunity to collaborate with global teams and OSAT partners.
  • Strong company culture (TAGIE) and commitment to innovation.
  • Competitive benefits package from a global semiconductor leader.
  • Requires deep expertise and 10+ years of experience, making entry difficult.
  • High responsibility for production quality and timely qualification.
  • May involve frequent communication with partners across time zones.
  • Ideal for experienced packaging engineers passionate about power electronics and advanced packaging innovation.

缺点 / 挑战

暂无明显挑战项

角色解读

  • Progress to technical expert or principal engineer in advanced packaging.
  • Move into team leadership or management roles in packaging R&D.
  • Expand into broader semiconductor integration and system-level design.
  • Develop and qualify advanced packaging solutions for power SiP modules, wafer-level, and flip-chip packages.
  • Collaborate with OSAT and contract manufacturers to optimize assembly processes and ensure quality production.
  • Drive package roadmap development and design rule establishment for power electronics.
  • Support product qualification and address customer complaints in cross-functional teams.
  • Deep knowledge of power SiP/module, wafer-level, and flip-chip packaging methods.
  • Experience in process development, DOE, SPC, and statistical analysis.
  • Strong communication and presentation skills for cross-team collaboration.
  • Familiarity with GaN-related packaging is a plus.

申请策略

  • Tailor your resume to match the specific requirements in the JD, using similar keywords.
  • Learn about Renesas's power product lines and their packaging roadmap to show genuine interest.
  • Highlight specific packaging development projects, especially power SiP or flip-chip.
  • Emphasize knowledge of DOE, SPC, and statistical tools.
  • Show experience with OSAT/CM collaboration and production ramp-up.
  • Include any GaN or wide-bandgap semiconductor packaging experience.
  • Review fundamentals of GaN packaging and thermal management.
  • Brush up on advanced packaging trends like panel-level packaging and hybrid bonding.

面试指南

  • Use STAR method: Situation, Task, Action, Result.
  • Quantify achievements and emphasize impact on yield, quality, or time-to-market.
  • Show systematic thinking and cross-functional collaboration.
  • Describe a challenging package development project you led and how you overcame process issues.
  • How do you approach DOE and process optimization for flip-chip assembly?
  • Explain your experience with power SiP or module packaging, and any GaN-specific challenges.
  • How do you ensure smooth ramp-up to production while maintaining quality?
  • Can you discuss your knowledge of SPC and statistical process control in packaging?

职位点评

67
综合评分

Advanced packaging role at a global semiconductor leader with strong technical challenges, competitive but undisclosed pay, and limited WLB transparency.

从薪资福利、成长空间、工作节奏和岗位方向综合评估，方便横向比较。

更适合这类人
Best suited for engineers prioritizing technical growth and meaningful work over lifestyle flexibility.
表现最好
成长发展
相对薄弱
工作生活
薪资福利60
成长发展85
工作生活50
使命价值70

薪资福利

60中等

The position likely offers competitive compensation given Renesas's global scale, but salary details are not disclosed in the JD.

薪资信号未披露（AI估算：40K-60K/月）

成长发展

85较高

This role involves advanced packaging technologies like power SiP and GaN, providing excellent technical growth opportunities.

技术前沿前沿/新兴技术
技术栈Power SiP、Wafer Level Packaging、Flip-chip、GaN、DOE、SPC
业务类型profit_center

工作生活

50较低

No explicit work-life balance signals; role likely requires on-site presence and may involve production-related pressure.

工作模式仅现场办公
办公地点未明确
加班情况未提及（无法判断）

使命价值

70中等

Renesas's purpose to 'Make Our Lives Easier' and its focus on automotive, industrial, and IoT provide a meaningful mission.

行业发展高速增长赛道
社会影响正向社会影响力较高
使命信号To Make Our Lives Easier、shaping a safer, healthier, greener, and smarter future
创新程度积极采用新技术

瑞萨电子 的其他在招职位

相似职位推荐

Watch Jobs