博通
R&D Engineer IC Design
R&D Engineer IC Design
发布于 大约 8 小时前普通员工/个人贡献者
上海市
中级经验
全职员工
仅现场办公
学历未注明
硬件工程
ASIC
RTL
STA
DRC
LVS
TCL
DFT
VLSI
CMOS
AI 估算 · 25k–40k
上海IC设计外企岗位，技术要求高，市场薪资竞争力强，参考行业中级工程师水平。
职位详情
关于这个职位
该职位是博通的IC设计研发工程师，负责ASIC全流程设计，包括综合、STA、物理实现等
你将参与28nm/16nm/7nm先进工艺节点项目，与内外客户合作开发尖端芯片解决方案，适合有扎实VLSI背景并追求技术深度的工程师
最低要求
Candidates should have good understanding about ASIC design flow and solid VLSI background.
Candidates should be able to handle block implementation/top level task independently.
Tapeout experience in 28nm and blow process design.
Candidates should have strong communications and problem solving skills.
工作职责
Full Chip Synthesis and STA: An ideal candidate should have some background on full chip synthesis flow (DC, DCT, DCG) for 16nm/7nm design tape out. It would be better if the candidate have the experience running full chip STA and constraint clean up flow.
Physical Design Implementation: An ideal candidate having some background in either the Physical Design which includes floor planning, placement, design closure, and DRC & LVS skills.
优先资格
DFT insertion
Power/IVD analysis
DRC/LVS
Candidate is good at Perl/Tcl
AI 洞察
暂无 AI 洞察数据
匹配度报告
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