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(Sr.) Staff Package Design Engineer - MIS substrate/FC expose die （ Experienced in Power or Gan is requried )
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(Sr.) Staff Package Design Engineer - MIS substrate/FC expose die （ Experienced in Power or Gan is requried )

发布于 大约 7 小时前

普通员工/个人贡献者

Zhubei, Taiwan
专家级经验
全职员工
仅现场办公
本科
硬件工程
Flip-Chip
Gan
Power Sip
Spc
Wafer Level Packaging
Multi-Chip Module
Wire-Bonding

AI 估算 · 40k–60k

高级封装设计工程师，10年以上经验，半导体行业薪酬较高，台湾地区资深岗位月薪约4-6万人民币。

职位详情

关于这个职位

这是一个高级封装设计工程师职位，主要负责电源SiP模块、晶圆级封装和倒装芯片等先进封装技术的开发与认证

您将与OSAT/CM合作优化工艺流程，确保产品良率与可靠性，并参与封装技术路线图的制定

最低要求

物理、化学、机械、电气或材料工程博士/硕士/学士学位

在封装开发方面拥有10年以上相关经验，重点在电源SiP/模块、晶圆级和倒装芯片封装
对电源SiP/模块、晶圆级/倒装芯片封装方法、组装工艺知识、鉴定方法、SPC和统计分析软件有深入了解
良好的人际交往和沟通能力
较强的分析和表达能力

工作职责

对标、选择并认证合适的材料、工艺和组装外包商（OSAT）或合同制造商（CM）

与OSAT/CM合作开发并执行DOE以优化工艺，建立工艺规范并监控和解决生产早期的工艺问题，确保只有优质零件交付给客户
与产品组和可靠性团队合作，在要求的时间框架内鉴定新封装和工艺，并与市场、产品、质量和运营部门的同事一起处理内外部客户投诉，以满足业务增长
确保平稳过渡到生产并实施爬坡监控
参与封装技术路线图的制定并专注于执行，发展和保持在电源SiP/模块、晶圆级封装、倒装芯片互连和面板级封装方面的技术专长和创新
建立和维护封装设计规则

优先资格

熟悉引线键合和多芯片模块技术者优先

有GaN相关封装经验者优先

AI 洞察

优缺点分析

优点

  • Work with world-leading semiconductor technology in automotive and industrial power applications.
  • High-impact role in a global company with strong engineering culture.
  • Opportunity to work on cutting-edge packaging technologies like GaN and SiP.
  • Competitive benefits package offered by Renesas.
  • Requires extensive experience (10+ years) and deep technical mastery.
  • Fast-paced environment with need to manage multiple OSAT/CM relationships and production issues.
  • High expectations for quality and reliability in automotive applications, demanding meticulous work.
  • This role is ideal for experienced packaging engineers with a strong background in power electronics and a passion for advanced packaging innovation.

缺点 / 挑战

暂无明显挑战项

角色解读

  • Progress to a technical leader or principal engineer in advanced packaging.
  • Expand expertise into emerging areas like GaN packaging and panel-level packaging.
  • Potential to move into packaging R&D management or product engineering leadership.
  • Develop and qualify advanced packaging technologies for power SiP, wafer-level, and flip-chip packages.
  • Collaborate with OSAT/CM to optimize assembly processes and ensure high-quality production.
  • Define package design rules and contribute to packaging roadmap.
  • Deep knowledge of power SiP/modules, wafer-level packaging, and flip-chip interconnects.
  • Experience in assembly process development, DOE, SPC, and statistical analysis.
  • Strong communication and presentation skills to work with cross-functional teams.

申请策略

  • Tailor your resume to emphasize power SiP/module, wafer-level, and flip-chip packaging expertise.
  • Research Renesas's product lines and packaging roadmap to align your experience with their needs.
  • Highlight your 10+ years of experience in package development, especially power SiP and flip-chip.
  • Emphasize your hands-on experience with OSAT/CM management and process optimization.
  • Showcase your knowledge of SPC, DOE, and statistical analysis tools.
  • If you lack GaN packaging experience, familiarize yourself with GaN device packaging challenges.
  • Strengthen your understanding of automotive-grade package qualification standards (AEC-Q).
  • Practice cross-functional communication and presentation skills.

面试指南

  • Use STAR method (Situation, Task, Action, Result) to structure your answers.
  • Highlight your technical depth and collaborative approach.
  • Show your understanding of statistical process control and quality standards.
  • Describe your experience in qualifying a new package for power applications.
  • How do you approach DOE for optimizing an assembly process?
  • Explain a time when you resolved a production issue with an OSAT.
  • What are the key challenges in GaN packaging?
  • How do you ensure package reliability for automotive applications?

职位点评

70
综合评分

Senior packaging engineering role in a global semiconductor leader, with cutting-edge technology and high compensation, but demanding work schedule.

从薪资福利、成长空间、工作节奏和岗位方向综合评估，方便横向比较。

更适合这类人
This role is best suited for engineers motivated by technical innovation and career growth, who are willing to work on-site and accept a demanding technical role.
表现最好
成长发展
相对薄弱
工作生活
薪资福利70
成长发展85
工作生活50
使命价值70

薪资福利

70中等

The position offers competitive salary and benefits typical for senior semiconductor roles in Taiwan, though exact figures are not disclosed in the JD.

薪资信号未披露（AI估算：40K-60K/月）

成长发展

85较高

This role provides exposure to cutting-edge packaging technologies like GaN and SiP, with significant opportunities for professional growth in a global company.

技术前沿前沿/新兴技术
技术栈Power SiP、Wafer Level Packaging、Flip-Chip、GaN、Multi-chip Module
业务类型ambiguous

工作生活

50较低

The role requires on-site work and likely frequent travel to OSAT/CM facilities, which may impact work-life balance.

工作模式仅现场办公
办公地点未明确
加班情况未提及（无法判断）

使命价值

70中等

The company emphasizes purpose and impact, but the role's direct societal impact is moderate, focusing on industrial and automotive power technology.

行业发展稳定成熟行业
社会影响中性/一般
使命信号To Make Our Lives Easier、shaping a safer, healthier, greener, and smarter future
创新程度积极采用新技术

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