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Copy of (Sr.) Staff Package Design Engineer - MIS substrate/FC expose die ( Experienced in Power or Gan is requried )

Copy of (Sr.) Staff Package Design Engineer - MIS substrate/FC expose die ( Experienced in Power or Gan is requried )

发布于 大约 7 小时前

普通员工/个人贡献者

Taichung City, Taiwan
专家级经验
全职员工
仅现场办公
本科
硬件工程
Doe
Flip-Chip
Gan
Osat
Power Sip
Spc
Wafer Level Packaging

AI 估算 · 40k–70k

Expert semiconductor packaging engineer with 10+ years experience, high demand for power/GaN expertise, competitive salary in Ta

职位详情

关于这个职位

This role is for a Senior Staff Package Design Engineer at Renesas, based in Taichung, Taiwan, focusing on the design and development of advanced semiconductor packaging for power applications, particularly power SiP/modules, wafer-level, and flip-chip technologies. The engineer will work with OSATs and CMs to develop and qualify new packages, ensuring high-quality, high-reliability products.

最低要求

Doctorate/Masters / Bachelor’s degree in Physics, Chemistry, Mechanical, Electrical or Materials Engineering.

>10 years of relevant experience in package development emphasizing power SiP/module, wafer level & flip-chip packaging.
Strong understanding of power SiP/modules, wafer level/flip-chip packaging methods, assembly process knowledge, qualification methods, SPC and statistical analysis software.
Strong interpersonal and communication skills.
Strong analytical and presentation skills.

工作职责

Benchmark, select and qualify suitable materials, processes and assembly subcontractors (OSAT) or contract manufacturers (CM).

Work with OSAT/CM to develop, run DOE to optimize processes, establish process spec & monitor and resolve process issues early in the production to ensure only parts with superior quality shipped to customer.
Work with Product groups and Reliability team, qualify new packages and processes within required time frame & further address internal and external customer complains working with peers of Marketing, Product groups, Quality and Operations organization to satisfy growth in businesses.
Ensure smooth transition into production & implement ramp up monitor.
Participate in packaging roadmap development & focus on execution, develop and maintain technical expertise on advances and innovations in power SiP/modules, wafer level packaging, flip chip interconnects and panel level package.
Establish & maintain package design rules.

优先资格

Knowledge of wire-bonding & multi-chip module technologies is a plus.

GaN related PKG is a plus.

AI 洞察

优缺点分析

优点

  • Work at the forefront of power semiconductor packaging, with high relevance to automotive and industrial markets.
  • Opportunity to collaborate with leading OSATs and internal global teams, building a strong professional network.
  • Competitive compensation typical for senior semiconductor engineering roles in Taiwan.
  • Contribute to innovative technologies like GaN, which are critical for future power efficiency.
  • + years of experience requirement means high expectations and responsibility for successful package qualifications.
  • May involve frequent travel or communication across different time zones with global partners.
  • Semiconductor packaging is complex and requires strong cross-functional coordination, which can be demanding.
  • This role suits experienced packaging engineers with a strong background in power electronics who thrive in cross-functional collaboration and want to make a tangible impact on next-gen power solutions.

缺点 / 挑战

暂无明显挑战项

角色解读

  • Progress to technical leadership roles such as Principal Engineer or technical fellow, leading packaging architecture decisions.
  • Expand expertise into advanced packaging technologies like chiplets, 2.5D/3D integration, and new wide-bandgap materials.
  • Move into management positions overseeing packaging development teams or cross-site engineering initiatives.
  • Develop and qualify advanced semiconductor packages, focusing on power SiP/modules, wafer-level, and flip-chip technologies.
  • Collaborate with OSAT/CM partners to run DOEs, optimize processes, and resolve production issues to ensure high-quality shipments.
  • Contribute to packaging roadmap development and maintain expertise in emerging technologies like GaN and panel-level packaging.
  • Establish and maintain package design rules to ensure reliability and manufacturability.
  • Deep understanding of power SiP/module, wafer-level, and flip-chip packaging methods and assembly processes.
  • Experience with qualification methods, SPC, and statistical analysis tools.
  • Strong communication and interpersonal skills to work with cross-functional teams and external partners.
  • Analytical and presentation skills to address customer issues and drive improvements.

申请策略

  • Tailor your resume to match the keywords in the JD, such as power SiP, flip-chip, and GaN.
  • Prepare to discuss specific examples of how you resolved process issues or collaborated with OSATs in past roles.
  • Highlight specific packaging development projects, especially power SiP/modules, wafer-level, or flip-chip packages.
  • Quantify achievements such as yield improvements, qualification success, or time-to-market reductions.
  • Showcase experience with GaN or other wide-bandgap technologies if applicable.
  • Emphasize experience working with OSATs, running DOEs, and using statistical analysis tools like JMP or Minitab.
  • Update knowledge on advanced packaging trends like panel-level packaging and hybrid bonding.
  • Familiarize with Power SiP/module design tools and thermal analysis if not already.

面试指南

  • For project-related questions, use the STAR method: Situation, Task, Action, Result, emphasizing your specific contributions.
  • When discussing technical methods, explain the rationale behind your choices and link them to business outcomes like yield, cost, or reliability.
  • For customer complaint scenarios, focus on root cause analysis, cross-functional collaboration, and preventive actions.
  • Describe a challenging package development project you led. What was the outcome?
  • How do you approach process optimization and DOE to reduce defects?
  • What experience do you have with GaN packaging? How is it different from silicon?
  • How do you ensure smooth technology transfer to mass production?
  • Can you explain a time you handled a customer complaint related to packaging quality?

职位点评

71
综合评分

Senior packaging engineering role with cutting-edge power/GaN technology, high compensation potential, but limited work-life balance signals.

从薪资福利、成长空间、工作节奏和岗位方向综合评估,方便横向比较。

更适合这类人
This role is ideal for experienced packaging engineers seeking deep technical challenges in power electronics and advanced packaging.
表现最好
成长发展
相对薄弱
工作生活
薪资福利75
成长发展85
工作生活45
使命价值70

薪资福利

75中等

The position likely offers competitive compensation in the semiconductor industry, though specific benefits are not detailed.

薪资信号未披露(AI估算:40K-70K/月)

成长发展

85较高

Cutting-edge packaging technologies for power electronics and GaN provide strong technical growth opportunities.

技术前沿前沿/新兴技术
技术栈Power SiP、Wafer Level Packaging、Flip-Chip、GaN、Panel Level Package
业务类型ambiguous

工作生活

45较低

Located in Taichung, Taiwan; no explicit work-life balance policies mentioned; semiconductor roles may involve occasional overtime.

工作模式未明确
办公地点未明确
加班情况未提及(无法判断)

使命价值

70中等

Renesas's mission to make lives easier and focus on automotive/industrial applications adds meaningful impact.

行业发展稳定成熟行业
社会影响中性/一般
使命信号To Make Our Lives Easier、shaping a safer, healthier, greener, and smarter future
创新程度积极采用新技术
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