博通
Staff Layout Engineer
Staff Layout Engineer
发布于 大约 14 小时前普通员工/个人贡献者
China-Shanghai-Zhangjiang Hi Tech
专家级经验
全职员工
仅现场办公
本科
芯片设计
Drc
Esd
Ic Layout
Lvs
Standard Cell
先进工艺节点
AI 估算 · 50k–80k
新加坡资深版图工程师，先进节点技能稀缺，薪资竞争力强。
职位详情
关于这个职位
该职位负责在先进工艺节点（如5nm/3nm）下进行标准单元、IO焊盘和混合信号IP的版图设计，需具备8年以上IC版图经验，精通Cadence Virtuoso和Calibre验证工具，并需立即前往新加坡工作
适合资深版图工程师寻求前沿技术挑战
最低要求
电子工程学士学位，至少8年IC版图经验
在标准单元、存储器、全定制和/或模拟/混合信号版图方面有深厚背景
对ESD和闩锁效应原理有扎实理解，适用于I/O设计
深入了解深亚微米/先进节点（如5nm、3nm、2nm、1.4nm）
熟练使用Cadence Virtuoso版图工具和Calibre物理验证（DRC、LVS、ERC、天线效应和EM/IR分析）
自我激励，能够独立工作，并且是强有力的团队合作者
能够主导新技术评审，编写版图方法学、版图流程和指南文档
在项目管理方面具有良好的领导素质
必须能够立即搬迁至新加坡
工作职责
版图设计与执行：应用设计指南和先进工艺规则，交付高性能、稳健的版图
规划与版图规划：独立管理进度，从晶体管级开始执行版图，包括单元级和模块级版图规划
协作与创新：快速适应新兴版图方法学，采纳新想法，并与所有站点工程师有效沟通
优先资格
具有脚本知识（Shell、Python、Tcl）或Cadence SKILL编程经验者优先
AI 洞察
优缺点分析
优点
- Work on advanced semiconductor nodes (5nm, 3nm, 2nm), which is highly valuable experience.
- Broadcom is a global leader in chip design, offering stable platform and resources.
- Opportunity to relocate to Singapore, a global tech hub with excellent living standards.
- Relocation is mandatory, which may be disruptive for family or personal life.
- High responsibility in delivering robust layouts under tight schedules.
- Requires continuous learning of new process rules and methodologies.
- Suitable for experienced IC layout engineers who seek frontier technology challenges and are open to international relocation.
缺点 / 挑战
暂无明显挑战项
角色解读
- Progress to Senior Staff or Principal Layout Engineer, leading complex IP layouts.
- Transition into layout methodology or CAD development roles.
- Opportunity to work on cutting-edge process nodes (1.4nm) and influence design flows.
- Design and execute high-quality layouts for standard cells, I/O pads, and mixed-signal IP in advanced process nodes.
- Perform cell- and block-level floorplanning from transistor level up, ensuring robust and high-performance layouts.
- Collaborate with global engineering teams and adapt to emerging layout methodologies.
- Deep expertise in IC layout, including Standard Cell, Memory, Full Custom, or Analog/Mixed-Signal blocks.
- Strong knowledge of advanced nodes (5nm, 3nm, 2nm) and ESD/Latch-up principles.
- Proficiency in Cadence Virtuoso and Calibre verification (DRC, LVS, ERC, EM/IR).
- Scripting skills (Shell/Python/Tcl) are a plus.
申请策略
- Tailor resume to align with the specific requirements of standard cell and mixed-signal layout.
- Be prepared to discuss relocation plans and availability for immediate onboarding.
- Highlight years of experience and specific process nodes (e.g., 5nm, 3nm) in layout projects.
- Emphasize proficiency in Cadence Virtuoso and Calibre verification, with concrete examples of DRC/LVS closure.
- Showcase any leadership in layout methodology reviews or project management.
- Brush up on scripting (Python/Tcl) and Cadence SKILL programming to stand out.
- Study ESD/Latch-up design principles and advanced node layout challenges.
面试指南
- Use the STAR method: situation, task, action, result, emphasizing your role and technical decisions.
- Demonstrate deep understanding of process rules by relating to specific examples from your projects.
- Show collaboration and leadership by highlighting cross-site communication and documentation skills.
- Describe a challenging layout project you handled in advanced nodes (e.g., 3nm). How did you ensure DRC/LVS cleanliness?
- How do you approach floorplanning for a mixed-signal block? What factors do you consider?
- Explain ESD and Latch-up considerations in I/O pad design.
- How do you stay updated with emerging layout methodologies and process rules?
- Tell us about a time you led a technology review and documented layout guidelines.
职位点评
70
综合评分
先进工艺版本的资深版图岗，技术前沿，高薪，但需现场办公并立即搬迁至新加坡。
从薪资福利、成长空间、工作节奏和岗位方向综合评估，方便横向比较。
更适合这类人
This position is best suited for experienced layout engineers who prioritize technical growth and are willing to relocate to Singapore for frontier chip design work.
表现最好
成长发展
相对薄弱
工作生活
薪资福利70
成长发展85
工作生活50
使命价值70
薪资福利
70中等
Although the salary is not disclosed, Broadcom typically offers competitive packages for senior roles. The absence of explicit benefits may be a minor factor.
薪资信号未披露（AI估算：50K-80K/月）
成长发展
85较高
This role offers deep exposure to cutting-edge process nodes (5nm/3nm/2nm) and advanced layout methodologies, which is highly valuable for career growth.
技术前沿前沿/新兴技术
技术栈Cadence Virtuoso、Calibre、DRC、LVS、ESD、5nm、3nm、2nm
业务类型ambiguous
工作生活
50较低
The role requires on-site work in Singapore and immediate relocation, which may impact work-life balance and personal convenience.
工作模式仅现场办公
办公地点海外（不适用）
加班情况未提及（无法判断）
使命价值
70中等
Working on advanced semiconductor technology contributes to technological progress, though the direct social impact is moderate.
行业发展高速增长赛道
社会影响中性/一般
创新程度积极采用新技术
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