Staff Layout Engineer
发布于 大约 14 小时前普通员工/个人贡献者
AI 估算 · 40k–65k
Senior IC layout role in Singapore, 8+ years experience, high salary converted to RMB.
职位详情
关于这个职位
As a Staff Layout Engineer, you will be responsible for executing high-quality layouts for Standard Cells, I/O pads, and Mixed-Signal IP across advanced process nodes. Working in Singapore, you'll collaborate with global teams and drive layout methodology improvements. This role requires deep expertise in IC physical design, ideally with 8+ years of experience.
最低要求
Education & Experience: Bachelor in Electronic Engineering with a minimum of 8 years of IC layout experience. Core Technical Expertise: Strong background in Standard Cell, Memory, Full Custom, and/or Analog/Mixed-Signal layout. Solid understanding of ESD and Latch-up principles for I/O design. Deep understanding of deep sub-micron / advanced nodes (e.g. 5nm, 3nm, 2nm, 1.4nm). Domain & Tool Knowledge: Proficient with Cadence Virtuoso layout tool and Calibre physical verification (DRC, LVS, ERC, Antenna, and EM/IR analysis). Personal Attributes: Self-motivated, capable of working independently, and a strong collaborative team player. Ability to lead on new technology reviews to compile documentation of layout methodology, layout flow and guidelines. Good leadership quality on project management. Re-location: Must be available for immediate relocation to Singapore.
工作职责
Layout Design & Execution: Apply design guidelines and advanced process rules to deliver high-performance, robust layouts. Planning & Floorplanning: Work independently to manage schedules and execute layouts from the transistor level up, including cell- and block-level floorplanning. Collaboration & Innovation: Adapt quickly to emerging layout methodologies, adopt new ideas, and communicate effectively with engineers across all sites.
优先资格
Scripting knowledge (Shell, Python, Tcl) or Cadence SKILL programming is a plus.
AI 洞察
优缺点分析
优点
- Cutting-edge process nodes provide exposure to the most advanced semiconductor technology.
- High compensation and global career opportunities at a top-tier company.
- Leadership responsibilities enhance project management skills.
- Must relocate to Singapore immediately, which may involve visa and lifestyle adjustments.
- High pressure to deliver error-free layouts under tight schedules.
- Requires continuous learning to keep up with shrinking node geometries.
- Ideal for experienced layout engineers seeking a challenging role at the forefront of IC design, willing to relocate to Singapore.
缺点 / 挑战
暂无明显挑战项
角色解读
- Progress to Principal Layout Engineer or CAD methodology lead.
- Transition to physical design management or chip integration roles.
- Deepen expertise in emerging process nodes (2nm, 1.4nm) and advanced packaging.
- Design and implement physical layouts for standard cells, I/O pads, and mixed-signal blocks using advanced process nodes.
- Perform floorplanning, placement, and routing at transistor level, ensuring design rule compliance.
- Collaborate with global teams and lead methodology reviews to improve layout flows.
- + years of IC layout experience with deep expertise in analog/mixed-signal and standard cell design.
- Proficiency with Cadence Virtuoso and Calibre verification (DRC/LVS/ERC/EM-IR).
- Understanding of ESD, latch-up, and advanced node effects (finFET, GAA).
- Strong communication and project leadership abilities.
申请策略
- Research Broadcom's product lines and their advanced node roadmap.
- Be ready to explain your willingness to relocate and any timeline.
- Highlight your years of experience and specific process nodes worked on (e.g., 5nm/3nm).
- Emphasize proficiency in Cadence and Calibre with examples of complex layout projects.
- Show leadership in guiding junior engineers or leading design reviews.
- Refresh scripting skills (Python/Tcl) to automate layout tasks.
- Learn about GAA transistor architecture if not familiar.
- Prepare to discuss ESD/latch-up design in detail.
面试指南
- Use the STAR method for behavioral questions: Situation, Task, Action, Result.
- Structure technical answers by problem, constraints, your approach, and outcome.
- Show awareness of trade-offs between performance, area, and power.
- How do you approach layout for a mixed-signal block in advanced nodes?
- Describe a challenging DRC rule issue you resolved.
- How do you ensure ESD design compliance in I/O layout?
- Explain your experience with EM/IR analysis.
- How do you lead a layout design review?
职位点评
A senior IC layout role with cutting-edge technology and high compensation, but requiring on-site work in Singapore and a demanding schedule.
从薪资福利、成长空间、工作节奏和岗位方向综合评估，方便横向比较。
薪资福利
This role offers a competitive salary and the financial stability of a large listed company, though exact compensation is not disclosed.
成长发展
This position provides exposure to cutting-edge process technologies and opportunities for technical leadership, fostering significant professional growth.
工作生活
The role requires relocation to Singapore and is primarily on-site, which may impact work-life balance due to relocation stress and potential overtime in a fast-paced industry.
使命价值
While working on advanced semiconductors contributes to technological progress, the direct social impact is limited, and the role is largely technical and engineering-focused.
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