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威睿
Staff Layout Engineer
立即应聘

Staff Layout Engineer

发布于 大约 14 小时前

普通员工/个人贡献者

China-Shanghai-Zhangjiang Hi Tech
专家级经验
全职员工
仅现场办公
学历未注明
芯片设计
Drc/Lvs/Erc
I/O
Memory Layout
Skill
Standard Cell
Virtuoso
7Nm/5Nm
Floor-Planning

AI 估算 · 45k–70k

Staff-level IC layout role with 8+ years required, based in Singapore, high market demand.

职位详情

关于这个职位

This is a senior IC layout engineering role focused on memory, I/O, and standard cell layout design. You will be based in Singapore and work on advanced process nodes (7nm, 5nm, 2nm) using Cadence Virtuoso and Calibre tools. The position requires deep expertise in physical verification and the ability to lead junior engineers.

最低要求

Strong layout knowledge with a minimum of 8 years of experience

Skills include Cadence layout, Cadence schematic capture, using CALIBRE & Hercules verification tools.
Strong layout knowledge in submicron processes, e.g. 16nm, 7nm, 5nm, 2nm, A14 and below
Experienced in digital (standard cell, memory, I/O) layout
Strong experience in memory layout design and physical verifications, including LVS, DRC, ERC, Antenna, and Electro Migration in CMOS processes.
Experienced in Cadence Layout tools VIRTUOSO (XL, VXL or EXL), and CALIBRE verification tools.
Good experience in Floor-planning, hierarchy layout and chip integration.
Able to lead or train a team of junior engineers
Good knowledge of memory layout topology.
Ability to lead new technology reviews to compile documentation of layout methodology, layout flow and guidelines.
Self-reliant, with the ability to work independently as well as in a team.
Good leadership quality in project management.
Must be available to re-locate to Singapore immediately.

工作职责

Responsible to understand and apply all necessary layout guidelines (standard cells, I/O memories), new process rules and other technical requirements for quality layout

Schedule time-line & layout floor-planning
Complete quality layout and verification within planned schedule (without supervision for experienced engineer)
Get up to speed quickly for new methodologies, open to new ideas and communicate well with others in the library team

优先资格

Experienced in analog layout is also a plus

Experience in memory compiler will be a plus
Knowledge of Script Programming and SKILL Programming would be a plus.

AI 洞察

优缺点分析

优点

  • Work on cutting-edge semiconductor process nodes (2nm and below).
  • Join a global leader (Broadcom) with a strong engineering culture.
  • Potential for high compensation in Singapore.
  • Opportunity to lead and mentor junior engineers.
  • Must relocate to Singapore immediately, involving significant lifestyle changes.
  • High responsibility for quality and schedule in complex layout tasks.
  • Requires continuous learning of new process rules and methodologies.
  • Experienced layout engineers who are self-reliant, adaptable, and seeking a senior technical role abroad.

缺点 / 挑战

暂无明显挑战项

角色解读

  • Advance to Senior Staff Engineer or Principal Engineer roles.
  • Move into technical management or architecture roles within the Library Group.
  • Become a domain expert in advanced node layout methodologies.
  • Design and verify physical layouts for memory, I/O, and standard cells using Cadence Virtuoso and Calibre.
  • Perform floor-planning, hierarchy layout, and chip integration for advanced process nodes.
  • Collaborate with circuit designers to ensure layout meets design rules and performance targets.
  • Lead new technology reviews and compile layout methodology documentation.
  • Strong command of Cadence Layout tools and CALIBRE/Hercules verification tools.
  • In-depth knowledge of submicron CMOS processes (16nm, 7nm, 5nm, 2nm, A14).
  • Expertise in memory layout design and physical verification (LVS, DRC, ERC, Antenna, EM).
  • Project leadership and team training abilities.

申请策略

  • Be ready to discuss your relocation plan to Singapore.
  • Demonstrate your ability to work independently and lead teams.
  • Emphasize 8+ years of IC layout experience with specific process nodes (7nm/5nm).
  • Highlight memory layout projects and physical verification achievements.
  • Showcase leadership in team training or project management.
  • Include any analog layout, SKILL programming, or memory compiler experience.
  • Strengthen Calibre/Hercules verification flow and advanced DRC/LVS debugging.
  • Learn SKILL scripting to automate layout tasks.

面试指南

  • Use the STAR method: situation, task, action, result.
  • Highlight your hands-on experience with specific tools and nodes.
  • Show your problem-solving and leadership qualities.
  • Describe a complex memory layout you designed. What were the challenges?
  • How do you ensure DRC/LVS clean sign-off under tight schedules?
  • Explain how you handle new process rule adoption.
  • How have you trained or mentored junior layout engineers?
  • What is your approach to floor-planning for a large chip?

职位点评

67
综合评分

Senior IC layout role at the technology frontier, requiring relocation to Singapore, with strong development potential but lifestyle disruptions.

从薪资福利、成长空间、工作节奏和岗位方向综合评估，方便横向比较。

更适合这类人
This role is best suited for motivated layout engineers who prioritize technical growth and career advancement and are willing to relocate to Singapore.
表现最好
成长发展
相对薄弱
工作生活
薪资福利65
成长发展85
工作生活40
使命价值75

薪资福利

65中等

The JD does not disclose salary, but the role is senior-level and based in Singapore, typically offering competitive compensation.

薪资信号未披露（AI估算：45K-70K/月）

成长发展

85较高

The role involves advanced process nodes, leadership opportunities, and technical depth, providing strong growth potential.

技术前沿前沿/新兴技术
技术栈Cadence、Virtuoso、Calibre、Hercules、DRC、LVS、ERC、Antenna、CMOS、2nm
业务类型ambiguous

工作生活

40较低

The immediate relocation requirement to Singapore may disrupt work-life balance, and no WLB signals are provided in the JD.

工作模式仅现场办公
办公地点未明确
加班情况未提及（无法判断）

使命价值

75中等

The semiconductor industry is booming, and the role contributes to advanced technology development, though no explicit mission statements are present.

行业发展高速增长赛道
社会影响中性/一般
创新程度积极采用新技术

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